powerpc: make dma_window_* in pci_controller struct avail on 32b
Also, convert them to resource_size_t (which is unsigned long on 64-bit, so it's not a change there). We will be using these on fsl 32b to indicate the start and size address of memory that the pci controller can actually reach - this is needed to determine if an address requires bounce buffering. For now, initialize them to a standard value; in the near future, the value will be calculated based on how the inbound windows are programmed. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -140,10 +140,12 @@ struct pci_controller {
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struct resource io_resource;
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struct resource io_resource;
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struct resource mem_resources[3];
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struct resource mem_resources[3];
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int global_number; /* PCI domain number */
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int global_number; /* PCI domain number */
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resource_size_t dma_window_base_cur;
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resource_size_t dma_window_size;
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#ifdef CONFIG_PPC64
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#ifdef CONFIG_PPC64
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unsigned long buid;
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unsigned long buid;
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unsigned long dma_window_base_cur;
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unsigned long dma_window_size;
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void *private_data;
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void *private_data;
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#endif /* CONFIG_PPC64 */
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#endif /* CONFIG_PPC64 */
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@ -152,6 +152,10 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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out_be32(&pci->piw[2].piwbar,0x00000000);
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out_be32(&pci->piw[2].piwbar,0x00000000);
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out_be32(&pci->piw[2].piwar, PIWAR_2G);
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out_be32(&pci->piw[2].piwar, PIWAR_2G);
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/* Save the base address and size covered by inbound window mappings */
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hose->dma_window_base_cur = 0x00000000;
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hose->dma_window_size = 0x80000000;
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iounmap(pci);
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iounmap(pci);
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}
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}
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