ARM: tegra: common clock framework fixes
A number of small fixes are included to the new Tegra common clock driver. These are: Missing locking, definition of device tree clock IDs not matching the binding, a static cleanup, missing initialization of some UART clocks. This branch is based on Tegra's previous pull request tegra-for-3.9-dt. This dependency is caused by the one patch that edits the device tree. If this causes a problem, I can drop the final two patches in this pull request for now, and rebase it onto previous tegra-for-3.9-soc-ccf instead. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRG9rSAAoJEMzrak5tbycxF/QP/icgj52RV0jnfMLHfClhXA7l x1o/OxrQOvN2rJtBRNHUYFasIgQONsSsarBvI3vtPVLHs5GccR6BMi291/palgL/ Rk0hB/8djZm/aFfELve2jrIbLpNc9++PVEkkhEMpViHe9EwcHC7YZA39cSQKvi62 +aZfjDizQRqE953o4sHdgoBGI0tU4Uf1WhnuAppzYVjvVHfHWe2h/D65n9Ir0bVH GohvyeGwqri03aJB+uNsdigVA11ZbpVG5jrkv77ZBxDhqDaM2iuFk9jhPXK3NW4B Tq5JgkosvQSrdnZceG7W6jaoPfdUIAVSKkVDa41Jm4Pe3MQsz3hewcKLrmbUHS1V L+IvqnK+PZ4iF4hPsRrTlOJAJzB7JWQyr6A9m+CCJ0onhRREzTSVrC9OMHOtZLv8 CnblH1TV2CwdUkbkB/vXqNH9vtXlupwOcRMDV0JgvcYW7chDWPVlmrSAYoTHuW1h FSeSgdFQdarG74nXmDE76GLSYtpFkQwacDJSxkdNZHyGyQlDNerqPPB02Fpg2MXh GbzMF0oXS4dLOniYXA82+sGuFhhK8Fe83jzefbDUuQSnzBz9FRKfCYAIxGZxyvRs 8813hXjMlWBdxECvuow5XiDaJ7719U6/IJ6uYS/JcQ3xr0oKtD9cSoZniSzBTjU6 kqM2cBU6EbsuxJXHhSS5 =vwx1 -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt ARM: tegra: common clock framework fixes A number of small fixes are included to the new Tegra common clock driver. These are: Missing locking, definition of device tree clock IDs not matching the binding, a static cleanup, missing initialization of some UART clocks. This branch is based on Tegra's previous pull request tegra-for-3.9-dt. This dependency is caused by the one patch that edits the device tree. If this causes a problem, I can drop the final two patches in this pull request for now, and rebase it onto previous tegra-for-3.9-soc-ccf instead. * tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: clk: tegra: initialise parent of uart clocks ARM: tegra: remove clock-frequency properties from serial nodes clk: tegra: fix driver to match DT binding clk: tegra: local arrays should be static clk: tegra: Add missing spinlock for hclk and pclk clk: tegra: Implement locking for super clock clk: tegra: fix wrong clock index between se to sata_cold (applied to next/dt branch rather than next/soc because of the dependency) Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
89dfe564b5
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@ -247,7 +247,6 @@
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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clock-frequency = <216000000>;
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nvidia,dma-request-selector = <&apbdma 8>;
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clocks = <&tegra_car 6>;
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status = "disabled";
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@ -258,7 +257,6 @@
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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clock-frequency = <216000000>;
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nvidia,dma-request-selector = <&apbdma 9>;
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clocks = <&tegra_car 96>;
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status = "disabled";
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@ -269,7 +267,6 @@
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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clock-frequency = <216000000>;
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nvidia,dma-request-selector = <&apbdma 10>;
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clocks = <&tegra_car 55>;
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status = "disabled";
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@ -280,7 +277,6 @@
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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clock-frequency = <216000000>;
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nvidia,dma-request-selector = <&apbdma 19>;
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clocks = <&tegra_car 65>;
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status = "disabled";
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@ -291,7 +287,6 @@
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = <0 91 0x04>;
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clock-frequency = <216000000>;
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nvidia,dma-request-selector = <&apbdma 20>;
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clocks = <&tegra_car 66>;
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status = "disabled";
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@ -234,7 +234,6 @@
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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clock-frequency = <408000000>;
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nvidia,dma-request-selector = <&apbdma 8>;
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clocks = <&tegra_car 6>;
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status = "disabled";
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@ -244,7 +243,6 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 37 0x04>;
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nvidia,dma-request-selector = <&apbdma 9>;
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clocks = <&tegra_car 160>;
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@ -255,7 +253,6 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 46 0x04>;
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nvidia,dma-request-selector = <&apbdma 10>;
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clocks = <&tegra_car 55>;
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@ -266,7 +263,6 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 90 0x04>;
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nvidia,dma-request-selector = <&apbdma 19>;
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clocks = <&tegra_car 65>;
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@ -277,7 +273,6 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 91 0x04>;
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nvidia,dma-request-selector = <&apbdma 20>;
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clocks = <&tegra_car 66>;
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@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
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u32 val, state;
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int err = 0;
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u8 parent_index, shift;
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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val = readl_relaxed(mux->reg);
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state = val & SUPER_STATE_MASK;
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@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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(index == mux->pllx_index))) {
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parent_index = clk_super_get_parent(hw);
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if ((parent_index == mux->div2_index) ||
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(parent_index == mux->pllx_index))
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return -EINVAL;
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(parent_index == mux->pllx_index)) {
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err = -EINVAL;
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goto out;
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}
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val ^= SUPER_LP_DIV2_BYPASS;
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writel_relaxed(val, mux->reg);
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@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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writel_relaxed(val, mux->reg);
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udelay(2);
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return 0;
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out:
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return err;
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}
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const struct clk_ops tegra_clk_super_ops = {
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@ -194,6 +194,7 @@ static void __iomem *clk_base;
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static void __iomem *pmc_base;
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static DEFINE_SPINLOCK(pll_div_lock);
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static DEFINE_SPINLOCK(sysrate_lock);
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#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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@ -239,8 +240,8 @@ enum tegra20_clk {
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uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
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osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
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pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
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pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
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pll_x, audio, pll_ref, twd, clk_max,
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pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
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pll_x, cop, audio, pll_ref, twd, clk_max,
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};
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static struct clk *clks[clk_max];
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@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void)
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/* HCLK */
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clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
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clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
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clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
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&sysrate_lock);
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clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
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clk_base + CLK_SYSTEM_RATE, 7,
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CLK_GATE_SET_TO_DISABLE, NULL);
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CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
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clk_register_clkdev(clk, "hclk", NULL);
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clks[hclk] = clk;
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/* PCLK */
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clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
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clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
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clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
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&sysrate_lock);
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clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
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clk_base + CLK_SYSTEM_RATE, 3,
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CLK_GATE_SET_TO_DISABLE, NULL);
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CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
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clk_register_clkdev(clk, "pclk", NULL);
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clks[pclk] = clk;
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@ -1251,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = {
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{csite, clk_max, 0, 1},
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{emc, clk_max, 0, 1},
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{cclk, clk_max, 0, 1},
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{uarta, pll_p, 0, 1},
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{uartd, pll_p, 0, 1},
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{uarta, pll_p, 0, 0},
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{uartb, pll_p, 0, 0},
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{uartc, pll_p, 0, 0},
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{uartd, pll_p, 0, 0},
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{uarte, pll_p, 0, 0},
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{usbd, clk_max, 12000000, 0},
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{usb2, clk_max, 12000000, 0},
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{usb3, clk_max, 12000000, 0},
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@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock);
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static DEFINE_SPINLOCK(pll_div_lock);
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static DEFINE_SPINLOCK(cml_lock);
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static DEFINE_SPINLOCK(pll_d_lock);
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static DEFINE_SPINLOCK(sysrate_lock);
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#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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@ -327,21 +328,21 @@ enum tegra30_clk {
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kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
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i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
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usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
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pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow,
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pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
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dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
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cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
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i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
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atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
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spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se,
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hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi,
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vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
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spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
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se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
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vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
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clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
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pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
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pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
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spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
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vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
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clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
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i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max
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hclk, pclk, clk_out_1_mux = 300, clk_max
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};
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static struct clk *clks[clk_max];
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@ -1249,16 +1250,16 @@ static void __init tegra30_pmc_clk_init(void)
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}
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const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p_cclkg", "pll_p_out4_cclkg",
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"pll_p_out3_cclkg", "unused", "pll_x" };
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const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p_cclklp", "pll_p_out4_cclklp",
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"pll_p_out3_cclklp", "unused", "pll_x",
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"pll_x_out0" };
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const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
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"pll_p_out3", "pll_p_out2", "unused",
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"clk_32k", "pll_m_out1" };
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static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p_cclkg", "pll_p_out4_cclkg",
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"pll_p_out3_cclkg", "unused", "pll_x" };
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static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p_cclklp", "pll_p_out4_cclklp",
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"pll_p_out3_cclklp", "unused", "pll_x",
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"pll_x_out0" };
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static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
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"pll_p_out3", "pll_p_out2", "unused",
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"clk_32k", "pll_m_out1" };
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static void __init tegra30_super_clk_init(void)
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{
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@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void)
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/* HCLK */
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clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
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clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
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clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
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&sysrate_lock);
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clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
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clk_base + SYSTEM_CLK_RATE, 7,
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CLK_GATE_SET_TO_DISABLE, NULL);
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CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
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clk_register_clkdev(clk, "hclk", NULL);
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clks[hclk] = clk;
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/* PCLK */
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clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
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clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
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clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
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&sysrate_lock);
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clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
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clk_base + SYSTEM_CLK_RATE, 3,
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CLK_GATE_SET_TO_DISABLE, NULL);
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CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
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clk_register_clkdev(clk, "pclk", NULL);
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clks[pclk] = clk;
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@ -1874,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
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};
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static __initdata struct tegra_clk_init_table init_table[] = {
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{uarta, pll_p, 408000000, 1},
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{uarta, pll_p, 408000000, 0},
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{uartb, pll_p, 408000000, 0},
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{uartc, pll_p, 408000000, 0},
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{uartd, pll_p, 408000000, 0},
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{uarte, pll_p, 408000000, 0},
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{pll_a, clk_max, 564480000, 1},
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{pll_a_out0, clk_max, 11289600, 1},
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{extern1, pll_a_out0, 0, 1},
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