Merge branch 'for-linus' of git://www.atmel.no/~hskinnemoen/linux/kernel/avr32
* 'for-linus' of git://www.atmel.no/~hskinnemoen/linux/kernel/avr32: [AVR32] Use per-controller spi_board_info structures [AVR32] Warn, don't BUG if clk_disable is called too many times [AVR32] Make sure all genclocks have a parent [AVR32] Remove unnecessary sys_nfsservctl conditional [AVR32] Wire up the SysV IPC calls properly [AVR32] Define ioremap_nocache, ioport_map and ioport_unmap [AVR32] Fix prototypes for __raw_writesb and friends
This commit is contained in:
Linus Torvalds
Коммит
8a03d9a498
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@ -8,7 +8,6 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -36,12 +35,11 @@ static struct eth_addr __initdata hw_addr[2];
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static struct eth_platform_data __initdata eth_data[2];
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extern struct lcdc_platform_data atstk1000_fb0_data;
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static struct spi_board_info spi_board_info[] __initdata = {
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static struct spi_board_info spi0_board_info[] __initdata = {
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{
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/* QVGA display */
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.modalias = "ltv350qv",
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.controller_data = (void *)GPIO_PIN_PA(4),
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.max_speed_hz = 16000000,
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.bus_num = 0,
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.chip_select = 1,
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},
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};
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@ -149,8 +147,7 @@ static int __init atstk1002_init(void)
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set_hw_addr(at32_add_device_eth(0, ð_data[0]));
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spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
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at32_add_device_spi(0);
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at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
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at32_add_device_lcdc(0, &atstk1000_fb0_data);
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return 0;
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@ -8,14 +8,6 @@
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* published by the Free Software Foundation.
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*/
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#if !defined(CONFIG_NFSD) && !defined(CONFIG_NFSD_MODULE)
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#define sys_nfsservctl sys_ni_syscall
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#endif
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#if !defined(CONFIG_SYSV_IPC)
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# define sys_ipc sys_ni_syscall
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#endif
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.section .rodata,"a",@progbits
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.type sys_call_table,@object
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.global sys_call_table
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@ -129,7 +121,7 @@ sys_call_table:
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.long sys_getitimer /* 105 */
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.long sys_swapoff
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.long sys_sysinfo
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.long sys_ipc
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.long sys_ni_syscall /* was sys_ipc briefly */
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.long sys_sendfile
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.long sys_setdomainname /* 110 */
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.long sys_newuname
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@ -287,4 +279,16 @@ sys_call_table:
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.long sys_tee
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.long sys_vmsplice
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.long __sys_epoll_pwait /* 265 */
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.long sys_msgget
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.long sys_msgsnd
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.long sys_msgrcv
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.long sys_msgctl
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.long sys_semget /* 270 */
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.long sys_semop
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.long sys_semctl
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.long sys_semtimedop
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.long sys_shmat
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.long sys_shmget /* 275 */
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.long sys_shmdt
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.long sys_shmctl
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.long sys_ni_syscall /* r8 is saturated at nr_syscalls */
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@ -8,6 +8,7 @@
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <asm/io.h>
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@ -310,8 +311,6 @@ static void genclk_mode(struct clk *clk, int enabled)
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{
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u32 control;
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BUG_ON(clk->index > 7);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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if (enabled)
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control |= SM_BIT(CEN);
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@ -325,11 +324,6 @@ static unsigned long genclk_get_rate(struct clk *clk)
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u32 control;
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unsigned long div = 1;
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BUG_ON(clk->index > 7);
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if (!clk->parent)
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return 0;
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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if (control & SM_BIT(DIVEN))
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div = 2 * (SM_BFEXT(DIV, control) + 1);
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@ -342,11 +336,6 @@ static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
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u32 control;
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unsigned long parent_rate, actual_rate, div;
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BUG_ON(clk->index > 7);
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if (!clk->parent)
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return 0;
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parent_rate = clk->parent->get_rate(clk->parent);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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@ -373,11 +362,8 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 control;
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BUG_ON(clk->index > 7);
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printk("clk %s: new parent %s (was %s)\n",
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clk->name, parent->name,
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clk->parent ? clk->parent->name : "(null)");
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clk->name, parent->name, clk->parent->name);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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@ -399,6 +385,22 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
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return 0;
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}
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static void __init genclk_init_parent(struct clk *clk)
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{
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u32 control;
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struct clk *parent;
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BUG_ON(clk->index > 7);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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if (control & SM_BIT(OSCSEL))
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parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
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else
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parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
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clk->parent = parent;
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}
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/* --------------------------------------------------------------------
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* System peripherals
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* -------------------------------------------------------------------- */
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@ -750,8 +752,41 @@ static struct resource atmel_spi1_resource[] = {
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DEFINE_DEV(atmel_spi, 1);
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DEV_CLK(spi_clk, atmel_spi1, pba, 1);
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struct platform_device *__init at32_add_device_spi(unsigned int id)
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static void
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at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
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unsigned int n, const u8 *pins)
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{
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unsigned int pin, mode;
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for (; n; n--, b++) {
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b->bus_num = bus_num;
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if (b->chip_select >= 4)
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continue;
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pin = (unsigned)b->controller_data;
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if (!pin) {
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pin = pins[b->chip_select];
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b->controller_data = (void *)pin;
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}
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mode = AT32_GPIOF_OUTPUT;
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if (!(b->mode & SPI_CS_HIGH))
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mode |= AT32_GPIOF_HIGH;
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at32_select_gpio(pin, mode);
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}
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}
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struct platform_device *__init
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at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
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{
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/*
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* Manage the chipselects as GPIOs, normally using the same pins
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* the SPI controller expects; but boards can use other pins.
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*/
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static u8 __initdata spi0_pins[] =
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{ GPIO_PIN_PA(3), GPIO_PIN_PA(4),
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GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
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static u8 __initdata spi1_pins[] =
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{ GPIO_PIN_PB(2), GPIO_PIN_PB(3),
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GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
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struct platform_device *pdev;
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switch (id) {
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@ -760,14 +795,7 @@ struct platform_device *__init at32_add_device_spi(unsigned int id)
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select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
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select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
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select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
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/* NPCS[2:0] */
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at32_select_gpio(GPIO_PIN_PA(3),
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_select_gpio(GPIO_PIN_PA(4),
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_select_gpio(GPIO_PIN_PA(5),
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_spi_setup_slaves(0, b, n, spi0_pins);
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break;
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case 1:
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@ -775,20 +803,14 @@ struct platform_device *__init at32_add_device_spi(unsigned int id)
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select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
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select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
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select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
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/* NPCS[2:0] */
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at32_select_gpio(GPIO_PIN_PB(2),
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_select_gpio(GPIO_PIN_PB(3),
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_select_gpio(GPIO_PIN_PB(4),
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_spi_setup_slaves(1, b, n, spi1_pins);
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break;
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default:
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return NULL;
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}
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spi_register_board_info(b, n);
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platform_device_register(pdev);
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return pdev;
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}
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@ -872,6 +894,50 @@ at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
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return pdev;
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}
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/* --------------------------------------------------------------------
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* GCLK
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* -------------------------------------------------------------------- */
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static struct clk gclk0 = {
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.name = "gclk0",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 0,
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};
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static struct clk gclk1 = {
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.name = "gclk1",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 1,
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};
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static struct clk gclk2 = {
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.name = "gclk2",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 2,
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};
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static struct clk gclk3 = {
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.name = "gclk3",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 3,
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};
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static struct clk gclk4 = {
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.name = "gclk4",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 4,
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};
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struct clk *at32_clock_list[] = {
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&osc32k,
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&osc0,
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@ -908,6 +974,11 @@ struct clk *at32_clock_list[] = {
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&atmel_spi1_spi_clk,
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&lcdc0_hclk,
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&lcdc0_pixclk,
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&gclk0,
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&gclk1,
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&gclk2,
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&gclk3,
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&gclk4,
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};
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unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
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@ -936,6 +1007,13 @@ void __init at32_clock_init(void)
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if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
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pll1.parent = &osc1;
|
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|
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genclk_init_parent(&gclk0);
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genclk_init_parent(&gclk1);
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genclk_init_parent(&gclk2);
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genclk_init_parent(&gclk3);
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genclk_init_parent(&gclk4);
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genclk_init_parent(&lcdc0_pixclk);
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/*
|
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* Turn on all clocks that have at least one user already, and
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* turn off everything else. We only do this for module
|
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|
|
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@ -63,7 +63,11 @@ EXPORT_SYMBOL(clk_enable);
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|
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static void __clk_disable(struct clk *clk)
|
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{
|
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BUG_ON(clk->users == 0);
|
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if (clk->users == 0) {
|
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printk(KERN_ERR "%s: mismatched disable\n", clk->name);
|
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WARN_ON(1);
|
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return;
|
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}
|
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|
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if (--clk->users == 0 && clk->mode)
|
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clk->mode(clk, 0);
|
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|
|
|
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|
|
@ -26,7 +26,9 @@ struct eth_platform_data {
|
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struct platform_device *
|
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at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
|
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|
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struct platform_device *at32_add_device_spi(unsigned int id);
|
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struct spi_board_info;
|
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struct platform_device *
|
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at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
|
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|
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struct lcdc_platform_data {
|
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unsigned long fbmem_start;
|
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|
|
|
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|
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@ -28,13 +28,13 @@ static __inline__ void * phys_to_virt(unsigned long address)
|
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* Generic IO read/write. These perform native-endian accesses. Note
|
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* that some architectures will want to re-define __raw_{read,write}w.
|
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*/
|
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extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
|
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extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
|
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extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
|
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extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
|
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extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
|
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extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
|
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|
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extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
|
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extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
|
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extern void __raw_readsl(unsigned int addr, void *data, int longlen);
|
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extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
|
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extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
|
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extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
|
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|
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static inline void writeb(unsigned char b, volatile void __iomem *addr)
|
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{
|
||||
|
|
@ -252,6 +252,9 @@ extern void __iounmap(void __iomem *addr);
|
|||
#define ioremap(offset, size) \
|
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__ioremap((offset), (size), 0)
|
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|
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#define ioremap_nocache(offset, size) \
|
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__ioremap((offset), (size), 0)
|
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|
||||
#define iounmap(addr) \
|
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__iounmap(addr)
|
||||
|
||||
|
|
@ -263,6 +266,14 @@ extern void __iounmap(void __iomem *addr);
|
|||
#define page_to_bus page_to_phys
|
||||
#define bus_to_page phys_to_page
|
||||
|
||||
/*
|
||||
* Create a virtual mapping cookie for an IO port range. There exists
|
||||
* no such thing as port-based I/O on AVR32, so a regular ioremap()
|
||||
* should do what we need.
|
||||
*/
|
||||
#define ioport_map(port, nr) ioremap(port, nr)
|
||||
#define ioport_unmap(port) iounmap(port)
|
||||
|
||||
#define dma_cache_wback_inv(_start, _size) \
|
||||
flush_dcache_region(_start, _size)
|
||||
#define dma_cache_inv(_start, _size) \
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@
|
|||
#define __NR_getitimer 105
|
||||
#define __NR_swapoff 106
|
||||
#define __NR_sysinfo 107
|
||||
#define __NR_ipc 108
|
||||
/* 108 was __NR_ipc for a little while */
|
||||
#define __NR_sendfile 109
|
||||
#define __NR_setdomainname 110
|
||||
#define __NR_uname 111
|
||||
|
|
@ -282,8 +282,21 @@
|
|||
#define __NR_vmsplice 264
|
||||
#define __NR_epoll_pwait 265
|
||||
|
||||
#define __NR_msgget 266
|
||||
#define __NR_msgsnd 267
|
||||
#define __NR_msgrcv 268
|
||||
#define __NR_msgctl 269
|
||||
#define __NR_semget 270
|
||||
#define __NR_semop 271
|
||||
#define __NR_semctl 272
|
||||
#define __NR_semtimedop 273
|
||||
#define __NR_shmat 274
|
||||
#define __NR_shmget 275
|
||||
#define __NR_shmdt 276
|
||||
#define __NR_shmctl 277
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#define NR_syscalls 266
|
||||
#define NR_syscalls 278
|
||||
|
||||
|
||||
#define __ARCH_WANT_IPC_PARSE_VERSION
|
||||
|
|
|
|||
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