[media] dvb-frontends/stv0367: make PLLSETUP a function, add 58MHz IC speed
This moves the PLL SETUP code from stv0367ter_init() into a dedicated function, and also make it possible to configure 58Mhz IC speed at 27MHz Xtal (used on STV0367-based DDB cards/modules in QAM mode). Signed-off-by: Daniel Scheller <d.scheller@gmx.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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8881ceb86f
Коммит
8a9c07359c
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@ -271,6 +271,53 @@ static void stv0367_write_table(struct stv0367_state *state,
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}
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}
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static void stv0367_pll_setup(struct stv0367_state *state,
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u32 icspeed, u32 xtal)
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{
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/* note on regs: R367TER_* and R367CAB_* defines each point to
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* 0xf0d8, so just use R367TER_ for both cases
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*/
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switch (icspeed) {
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case STV0367_ICSPEED_58000:
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switch (xtal) {
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default:
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case 27000000:
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dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
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/* PLLMDIV: 27, PLLNDIV: 232 */
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stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
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stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
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break;
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}
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break;
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default:
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case STV0367_ICSPEED_53125:
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switch (xtal) {
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/* set internal freq to 53.125MHz */
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case 16000000:
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stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
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break;
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case 25000000:
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stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
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break;
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default:
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case 27000000:
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dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
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stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
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break;
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case 30000000:
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stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
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break;
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}
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}
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stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
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}
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static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
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{
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struct stv0367_state *state = fe->demodulator_priv;
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@ -918,31 +965,7 @@ static int stv0367ter_init(struct dvb_frontend *fe)
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stv0367_write_table(state,
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stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
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switch (state->config->xtal) {
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/*set internal freq to 53.125MHz */
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case 16000000:
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stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
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stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
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break;
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case 25000000:
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stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
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stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
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break;
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default:
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case 27000000:
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dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
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stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
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stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
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break;
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case 30000000:
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stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
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stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
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stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
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break;
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}
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stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
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stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
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stv0367_writereg(state, R367TER_ANACTRL, 0x00);
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@ -25,6 +25,9 @@
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#include <linux/dvb/frontend.h>
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#include "dvb_frontend.h"
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#define STV0367_ICSPEED_53125 53125000
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#define STV0367_ICSPEED_58000 58000000
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struct stv0367_config {
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u8 demod_address;
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u32 xtal;
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