spi: sh-msiof: Do not redefine STR while compile testing
STR is a well-known stringify macro so it should be avoided in drivers
to avoid warnings like this (MIPS architecture while compile testing):
drivers/spi/spi-sh-msiof.c:76:0: warning: "STR" redefined
#define STR 0x40 /* Status Register */
arch/mips/include/asm/mipsregs.h:30:0: note: this is the location of the previous definition
#define STR(x) __STR(x)
To maintain consistency between all register names add a SI prefix to
all of them. This also matches register names in datasheet.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200108194319.3171-1-krzk@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Mark Brown
Родитель
144d8f9781
Коммит
8ae7d44239
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@ -60,140 +60,140 @@ struct sh_msiof_spi_priv {
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#define MAX_SS 3 /* Maximum number of native chip selects */
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#define TMDR1 0x00 /* Transmit Mode Register 1 */
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#define TMDR2 0x04 /* Transmit Mode Register 2 */
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#define TMDR3 0x08 /* Transmit Mode Register 3 */
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#define RMDR1 0x10 /* Receive Mode Register 1 */
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#define RMDR2 0x14 /* Receive Mode Register 2 */
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#define RMDR3 0x18 /* Receive Mode Register 3 */
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#define TSCR 0x20 /* Transmit Clock Select Register */
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#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
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#define CTR 0x28 /* Control Register */
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#define FCTR 0x30 /* FIFO Control Register */
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#define STR 0x40 /* Status Register */
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#define IER 0x44 /* Interrupt Enable Register */
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#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
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#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
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#define TFDR 0x50 /* Transmit FIFO Data Register */
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#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
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#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
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#define RFDR 0x60 /* Receive FIFO Data Register */
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#define SITMDR1 0x00 /* Transmit Mode Register 1 */
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#define SITMDR2 0x04 /* Transmit Mode Register 2 */
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#define SITMDR3 0x08 /* Transmit Mode Register 3 */
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#define SIRMDR1 0x10 /* Receive Mode Register 1 */
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#define SIRMDR2 0x14 /* Receive Mode Register 2 */
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#define SIRMDR3 0x18 /* Receive Mode Register 3 */
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#define SITSCR 0x20 /* Transmit Clock Select Register */
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#define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
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#define SICTR 0x28 /* Control Register */
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#define SIFCTR 0x30 /* FIFO Control Register */
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#define SISTR 0x40 /* Status Register */
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#define SIIER 0x44 /* Interrupt Enable Register */
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#define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
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#define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
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#define SITFDR 0x50 /* Transmit FIFO Data Register */
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#define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
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#define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
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#define SIRFDR 0x60 /* Receive FIFO Data Register */
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/* TMDR1 and RMDR1 */
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#define MDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
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#define MDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
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#define MDR1_SYNCMD_SPI (2 << 28)/* Level mode/SPI */
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#define MDR1_SYNCMD_LR (3 << 28)/* L/R mode */
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#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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#define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
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#define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
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#define MDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
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#define MDR1_FLD_SHIFT 2
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#define MDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
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/* TMDR1 */
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#define TMDR1_PCON BIT(30) /* Transfer Signal Connection */
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#define TMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
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#define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
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/* SITMDR1 and SIRMDR1 */
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#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
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#define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
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#define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
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#define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */
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#define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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#define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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#define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
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#define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
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#define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
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#define SIMDR1_FLD_SHIFT 2
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#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
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/* SITMDR1 */
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#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
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#define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
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#define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
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/* TMDR2 and RMDR2 */
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#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
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#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
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#define MDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */
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/* SITMDR2 and SIRMDR2 */
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#define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
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#define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
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#define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */
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/* TSCR and RSCR */
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#define SCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */
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#define SCR_BRPS(i) (((i) - 1) << 8)
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#define SCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
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#define SCR_BRDV_DIV_2 0
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#define SCR_BRDV_DIV_4 1
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#define SCR_BRDV_DIV_8 2
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#define SCR_BRDV_DIV_16 3
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#define SCR_BRDV_DIV_32 4
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#define SCR_BRDV_DIV_1 7
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/* SITSCR and SIRSCR */
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#define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */
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#define SISCR_BRPS(i) (((i) - 1) << 8)
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#define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
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#define SISCR_BRDV_DIV_2 0
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#define SISCR_BRDV_DIV_4 1
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#define SISCR_BRDV_DIV_8 2
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#define SISCR_BRDV_DIV_16 3
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#define SISCR_BRDV_DIV_32 4
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#define SISCR_BRDV_DIV_1 7
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/* CTR */
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#define CTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
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#define CTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
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#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
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#define CTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
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#define CTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
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#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
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#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
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#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
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#define CTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */
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#define CTR_TXDIZ_LOW (0 << 22) /* 0 */
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#define CTR_TXDIZ_HIGH (1 << 22) /* 1 */
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#define CTR_TXDIZ_HIZ (2 << 22) /* High-impedance */
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#define CTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
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#define CTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
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#define CTR_TXE BIT(9) /* Transmit Enable */
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#define CTR_RXE BIT(8) /* Receive Enable */
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#define CTR_TXRST BIT(1) /* Transmit Reset */
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#define CTR_RXRST BIT(0) /* Receive Reset */
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/* SICTR */
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#define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
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#define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
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#define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
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#define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
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#define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
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#define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
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#define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
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#define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
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#define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */
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#define SICTR_TXDIZ_LOW (0 << 22) /* 0 */
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#define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */
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#define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */
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#define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
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#define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
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#define SICTR_TXE BIT(9) /* Transmit Enable */
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#define SICTR_RXE BIT(8) /* Receive Enable */
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#define SICTR_TXRST BIT(1) /* Transmit Reset */
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#define SICTR_RXRST BIT(0) /* Receive Reset */
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/* FCTR */
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#define FCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
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#define FCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */
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#define FCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */
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#define FCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */
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#define FCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */
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#define FCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */
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#define FCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */
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#define FCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */
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#define FCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */
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#define FCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */
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#define FCTR_TFUA_SHIFT 20
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#define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
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#define FCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */
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#define FCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
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#define FCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
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#define FCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
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#define FCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
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#define FCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
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#define FCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
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#define FCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
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#define FCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */
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#define FCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
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#define FCTR_RFUA_SHIFT 4
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#define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
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/* SIFCTR */
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#define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
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#define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */
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#define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */
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#define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */
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#define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */
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#define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */
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#define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */
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#define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */
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#define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */
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#define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */
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#define SIFCTR_TFUA_SHIFT 20
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#define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT)
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#define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */
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#define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
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#define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
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#define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
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#define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
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#define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
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#define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
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#define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
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#define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */
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#define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
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#define SIFCTR_RFUA_SHIFT 4
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#define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT)
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/* STR */
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#define STR_TFEMP BIT(29) /* Transmit FIFO Empty */
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#define STR_TDREQ BIT(28) /* Transmit Data Transfer Request */
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#define STR_TEOF BIT(23) /* Frame Transmission End */
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#define STR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
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#define STR_TFOVF BIT(20) /* Transmit FIFO Overflow */
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#define STR_TFUDF BIT(19) /* Transmit FIFO Underflow */
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#define STR_RFFUL BIT(13) /* Receive FIFO Full */
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#define STR_RDREQ BIT(12) /* Receive Data Transfer Request */
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#define STR_REOF BIT(7) /* Frame Reception End */
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#define STR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
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#define STR_RFUDF BIT(4) /* Receive FIFO Underflow */
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#define STR_RFOVF BIT(3) /* Receive FIFO Overflow */
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/* SISTR */
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#define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
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#define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
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#define SISTR_TEOF BIT(23) /* Frame Transmission End */
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#define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
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#define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
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#define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
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#define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
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#define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
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#define SISTR_REOF BIT(7) /* Frame Reception End */
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#define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
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#define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
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#define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
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/* IER */
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#define IER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
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#define IER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
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#define IER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
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#define IER_TEOFE BIT(23) /* Frame Transmission End Enable */
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#define IER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
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#define IER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
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#define IER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
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#define IER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
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#define IER_RFFULE BIT(13) /* Receive FIFO Full Enable */
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#define IER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
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#define IER_REOFE BIT(7) /* Frame Reception End Enable */
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#define IER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
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#define IER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
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#define IER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
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/* SIIER */
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#define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
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#define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
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#define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
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#define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
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#define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
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#define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
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#define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
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#define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
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#define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
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#define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
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#define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
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#define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
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#define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
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#define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
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static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
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{
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switch (reg_offs) {
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case TSCR:
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case RSCR:
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case SITSCR:
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case SIRSCR:
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return ioread16(p->mapbase + reg_offs);
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default:
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return ioread32(p->mapbase + reg_offs);
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@ -204,8 +204,8 @@ static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
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u32 value)
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{
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switch (reg_offs) {
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case TSCR:
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case RSCR:
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case SITSCR:
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case SIRSCR:
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iowrite16(value, p->mapbase + reg_offs);
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break;
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default:
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@ -220,12 +220,12 @@ static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
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u32 mask = clr | set;
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u32 data;
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data = sh_msiof_read(p, CTR);
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data = sh_msiof_read(p, SICTR);
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data &= ~clr;
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data |= set;
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sh_msiof_write(p, CTR, data);
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sh_msiof_write(p, SICTR, data);
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return readl_poll_timeout_atomic(p->mapbase + CTR, data,
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return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
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(data & mask) == set, 1, 100);
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}
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|
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@ -234,7 +234,7 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
|
|||
struct sh_msiof_spi_priv *p = data;
|
||||
|
||||
/* just disable the interrupt and wake up */
|
||||
sh_msiof_write(p, IER, 0);
|
||||
sh_msiof_write(p, SIIER, 0);
|
||||
complete(&p->done);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -242,20 +242,20 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
|
|||
|
||||
static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
|
||||
{
|
||||
u32 mask = CTR_TXRST | CTR_RXRST;
|
||||
u32 mask = SICTR_TXRST | SICTR_RXRST;
|
||||
u32 data;
|
||||
|
||||
data = sh_msiof_read(p, CTR);
|
||||
data = sh_msiof_read(p, SICTR);
|
||||
data |= mask;
|
||||
sh_msiof_write(p, CTR, data);
|
||||
sh_msiof_write(p, SICTR, data);
|
||||
|
||||
readl_poll_timeout_atomic(p->mapbase + CTR, data, !(data & mask), 1,
|
||||
readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
|
||||
100);
|
||||
}
|
||||
|
||||
static const u32 sh_msiof_spi_div_array[] = {
|
||||
SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
|
||||
SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
|
||||
SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
|
||||
SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
|
||||
};
|
||||
|
||||
static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -273,7 +273,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
|
|||
|
||||
div = DIV_ROUND_UP(parent_rate, spi_hz);
|
||||
if (div <= 1024) {
|
||||
/* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
|
||||
/* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
|
||||
if (!div_pow && div <= 32 && div > 2)
|
||||
div_pow = 1;
|
||||
|
||||
|
|
@ -292,10 +292,10 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
|
|||
brps = 32;
|
||||
}
|
||||
|
||||
scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
|
||||
sh_msiof_write(p, TSCR, scr);
|
||||
scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
|
||||
sh_msiof_write(p, SITSCR, scr);
|
||||
if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
|
||||
sh_msiof_write(p, RSCR, scr);
|
||||
sh_msiof_write(p, SIRSCR, scr);
|
||||
}
|
||||
|
||||
static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
|
||||
|
|
@ -334,8 +334,8 @@ static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
|
|||
return 0;
|
||||
}
|
||||
|
||||
val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
|
||||
val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
|
||||
val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
|
||||
val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
|
@ -354,54 +354,54 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
|
|||
* 1 0 11 11 0 0
|
||||
* 1 1 11 11 1 1
|
||||
*/
|
||||
tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
|
||||
tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
|
||||
tmp |= lsb_first << MDR1_BITLSB_SHIFT;
|
||||
tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
|
||||
tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
|
||||
tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
|
||||
tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
|
||||
if (spi_controller_is_slave(p->ctlr)) {
|
||||
sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
|
||||
sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
|
||||
} else {
|
||||
sh_msiof_write(p, TMDR1,
|
||||
tmp | MDR1_TRMD | TMDR1_PCON |
|
||||
(ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
|
||||
sh_msiof_write(p, SITMDR1,
|
||||
tmp | SIMDR1_TRMD | SITMDR1_PCON |
|
||||
(ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
|
||||
}
|
||||
if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
|
||||
/* These bits are reserved if RX needs TX */
|
||||
tmp &= ~0x0000ffff;
|
||||
}
|
||||
sh_msiof_write(p, RMDR1, tmp);
|
||||
sh_msiof_write(p, SIRMDR1, tmp);
|
||||
|
||||
tmp = 0;
|
||||
tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
|
||||
tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
|
||||
tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
|
||||
tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
|
||||
|
||||
edge = cpol ^ !cpha;
|
||||
|
||||
tmp |= edge << CTR_TEDG_SHIFT;
|
||||
tmp |= edge << CTR_REDG_SHIFT;
|
||||
tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
|
||||
sh_msiof_write(p, CTR, tmp);
|
||||
tmp |= edge << SICTR_TEDG_SHIFT;
|
||||
tmp |= edge << SICTR_REDG_SHIFT;
|
||||
tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
|
||||
sh_msiof_write(p, SICTR, tmp);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
|
||||
const void *tx_buf, void *rx_buf,
|
||||
u32 bits, u32 words)
|
||||
{
|
||||
u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
|
||||
u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
|
||||
|
||||
if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
|
||||
sh_msiof_write(p, TMDR2, dr2);
|
||||
sh_msiof_write(p, SITMDR2, dr2);
|
||||
else
|
||||
sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
|
||||
sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
|
||||
|
||||
if (rx_buf)
|
||||
sh_msiof_write(p, RMDR2, dr2);
|
||||
sh_msiof_write(p, SIRMDR2, dr2);
|
||||
}
|
||||
|
||||
static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
|
||||
{
|
||||
sh_msiof_write(p, STR,
|
||||
sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
|
||||
sh_msiof_write(p, SISTR,
|
||||
sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -411,7 +411,7 @@ static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, buf_8[k] << fs);
|
||||
sh_msiof_write(p, SITFDR, buf_8[k] << fs);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -421,7 +421,7 @@ static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, buf_16[k] << fs);
|
||||
sh_msiof_write(p, SITFDR, buf_16[k] << fs);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -431,7 +431,7 @@ static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
|
||||
sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -441,7 +441,7 @@ static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, buf_32[k] << fs);
|
||||
sh_msiof_write(p, SITFDR, buf_32[k] << fs);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -451,7 +451,7 @@ static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
|
||||
sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -461,7 +461,7 @@ static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
|
||||
sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -471,7 +471,7 @@ static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
|
||||
sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -481,7 +481,7 @@ static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
|
||||
buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -491,7 +491,7 @@ static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
|
||||
buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -501,7 +501,7 @@ static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
|
||||
put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -511,7 +511,7 @@ static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
|
||||
buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -521,7 +521,7 @@ static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
|
||||
put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -531,7 +531,7 @@ static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
|
||||
buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
|
||||
}
|
||||
|
||||
static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
|
||||
|
|
@ -541,7 +541,7 @@ static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
|
|||
int k;
|
||||
|
||||
for (k = 0; k < words; k++)
|
||||
put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
|
||||
put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
|
||||
}
|
||||
|
||||
static int sh_msiof_spi_setup(struct spi_device *spi)
|
||||
|
|
@ -558,17 +558,17 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
|
|||
return 0;
|
||||
|
||||
/* Configure native chip select mode/polarity early */
|
||||
clr = MDR1_SYNCMD_MASK;
|
||||
set = MDR1_SYNCMD_SPI;
|
||||
clr = SIMDR1_SYNCMD_MASK;
|
||||
set = SIMDR1_SYNCMD_SPI;
|
||||
if (spi->mode & SPI_CS_HIGH)
|
||||
clr |= BIT(MDR1_SYNCAC_SHIFT);
|
||||
clr |= BIT(SIMDR1_SYNCAC_SHIFT);
|
||||
else
|
||||
set |= BIT(MDR1_SYNCAC_SHIFT);
|
||||
set |= BIT(SIMDR1_SYNCAC_SHIFT);
|
||||
pm_runtime_get_sync(&p->pdev->dev);
|
||||
tmp = sh_msiof_read(p, TMDR1) & ~clr;
|
||||
sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
|
||||
tmp = sh_msiof_read(p, RMDR1) & ~clr;
|
||||
sh_msiof_write(p, RMDR1, tmp | set);
|
||||
tmp = sh_msiof_read(p, SITMDR1) & ~clr;
|
||||
sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
|
||||
tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
|
||||
sh_msiof_write(p, SIRMDR1, tmp | set);
|
||||
pm_runtime_put(&p->pdev->dev);
|
||||
p->native_cs_high = spi->mode & SPI_CS_HIGH;
|
||||
p->native_cs_inited = true;
|
||||
|
|
@ -604,15 +604,15 @@ static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
|
|||
|
||||
/* setup clock and rx/tx signals */
|
||||
if (!slave)
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
|
||||
if (rx_buf && !ret)
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
|
||||
if (!ret)
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
|
||||
|
||||
/* start by setting frame bit */
|
||||
if (!ret && !slave)
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
|
||||
ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -624,13 +624,13 @@ static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
|
|||
|
||||
/* shut down frame, rx/tx and clock signals */
|
||||
if (!slave)
|
||||
ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
|
||||
ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
|
||||
if (!ret)
|
||||
ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
|
||||
ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
|
||||
if (rx_buf && !ret)
|
||||
ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
|
||||
ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
|
||||
if (!ret && !slave)
|
||||
ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
|
||||
ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -685,11 +685,11 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
|
|||
fifo_shift = 32 - bits;
|
||||
|
||||
/* default FIFO watermarks for PIO */
|
||||
sh_msiof_write(p, FCTR, 0);
|
||||
sh_msiof_write(p, SIFCTR, 0);
|
||||
|
||||
/* setup msiof transfer mode registers */
|
||||
sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
|
||||
sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
|
||||
sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
|
||||
|
||||
/* write tx fifo */
|
||||
if (tx_buf)
|
||||
|
|
@ -728,7 +728,7 @@ stop_reset:
|
|||
sh_msiof_reset_str(p);
|
||||
sh_msiof_spi_stop(p, rx_buf);
|
||||
stop_ier:
|
||||
sh_msiof_write(p, IER, 0);
|
||||
sh_msiof_write(p, SIIER, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -747,7 +747,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
|
|||
|
||||
/* First prepare and submit the DMA request(s), as this may fail */
|
||||
if (rx) {
|
||||
ier_bits |= IER_RDREQE | IER_RDMAE;
|
||||
ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
|
||||
desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
|
||||
p->rx_dma_addr, len, DMA_DEV_TO_MEM,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
|
|
@ -762,7 +762,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
|
|||
}
|
||||
|
||||
if (tx) {
|
||||
ier_bits |= IER_TDREQE | IER_TDMAE;
|
||||
ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
|
||||
dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
|
||||
p->tx_dma_addr, len, DMA_TO_DEVICE);
|
||||
desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
|
||||
|
|
@ -783,12 +783,12 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
|
|||
}
|
||||
|
||||
/* 1 stage FIFO watermarks for DMA */
|
||||
sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
|
||||
sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
|
||||
|
||||
/* setup msiof transfer mode registers (32-bit words) */
|
||||
sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
|
||||
|
||||
sh_msiof_write(p, IER, ier_bits);
|
||||
sh_msiof_write(p, SIIER, ier_bits);
|
||||
|
||||
reinit_completion(&p->done);
|
||||
if (tx)
|
||||
|
|
@ -820,10 +820,10 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
|
|||
if (ret)
|
||||
goto stop_reset;
|
||||
|
||||
sh_msiof_write(p, IER, 0);
|
||||
sh_msiof_write(p, SIIER, 0);
|
||||
} else {
|
||||
/* wait for tx fifo to be emptied */
|
||||
sh_msiof_write(p, IER, IER_TEOFE);
|
||||
sh_msiof_write(p, SIIER, SIIER_TEOFE);
|
||||
ret = sh_msiof_wait_for_completion(p, &p->done);
|
||||
if (ret)
|
||||
goto stop_reset;
|
||||
|
|
@ -853,7 +853,7 @@ stop_dma:
|
|||
no_dma_tx:
|
||||
if (rx)
|
||||
dmaengine_terminate_all(p->ctlr->dma_rx);
|
||||
sh_msiof_write(p, IER, 0);
|
||||
sh_msiof_write(p, SIIER, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1189,12 +1189,12 @@ static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
|
|||
|
||||
ctlr = p->ctlr;
|
||||
ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
|
||||
dma_tx_id, res->start + TFDR);
|
||||
dma_tx_id, res->start + SITFDR);
|
||||
if (!ctlr->dma_tx)
|
||||
return -ENODEV;
|
||||
|
||||
ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
|
||||
dma_rx_id, res->start + RFDR);
|
||||
dma_rx_id, res->start + SIRFDR);
|
||||
if (!ctlr->dma_rx)
|
||||
goto free_tx_chan;
|
||||
|
||||
|
|
|
|||
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