OMAP: DSS2: DSI Video mode support
Add initial support for DSI video mode panels: - Add a new structure omap_dss_dsi_videomode_data in the member "panel" in omap_dss_device struct. This allows panel driver to configure dsi video_mode specific parameters. - Configure basic DSI video mode timing parameters: HBP, HFP, HSA, VBP, VFP, VSA, TL and VACT. - Configure DSI protocol engine registers for video_mode support. - Introduce functions dsi_video_mode_enable() and dsi_video_mode_disable() which enable/disable video mode for a given virtual channel and a given pixel format type. Things left for later - Add functions to check for errors in video mode timings provided by panel. - Configure timing registers required for command mode interleaving. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Archit Taneja
Tomi Valkeinen
Родитель
18b7d09908
Коммит
8af6ff0107
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@ -132,7 +132,7 @@ struct dsi_reg { u16 idx; };
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#define DSI_IRQ_TA_TIMEOUT (1 << 20)
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#define DSI_IRQ_ERROR_MASK \
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(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
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DSI_IRQ_TA_TIMEOUT)
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DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
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#define DSI_IRQ_CHANNEL_MASK 0xf
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/* Virtual channel interrupts */
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@ -2472,6 +2472,12 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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dsi_cio_timings(dsidev);
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
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/* DDR_CLK_ALWAYS_ON */
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REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
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dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
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}
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dsi->ulps_enabled = false;
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DSSDBG("CIO init done\n");
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@ -2496,6 +2502,9 @@ static void dsi_cio_uninit(struct omap_dss_device *dssdev)
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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/* DDR_CLK_ALWAYS_ON */
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REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
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dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
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dsi_disable_scp_clk(dsidev);
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dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
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@ -2799,6 +2808,10 @@ void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
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dsi_if_enable(dsidev, 1);
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dsi_force_tx_stop_mode_io(dsidev);
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/* start the DDR clock by sending a NULL packet */
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if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
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dsi_vc_send_null(dssdev, channel);
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}
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EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
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@ -3682,6 +3695,75 @@ static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
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ticks, x4 ? " x4" : "", x16 ? " x16" : "",
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(total_ticks * 1000) / (fck / 1000 / 1000));
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}
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static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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int num_line_buffers;
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
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struct omap_video_timings *timings = &dssdev->panel.timings;
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/*
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* Don't use line buffers if width is greater than the video
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* port's line buffer size
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*/
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if (line_buf_size <= timings->x_res * bpp / 8)
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num_line_buffers = 0;
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else
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num_line_buffers = 2;
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} else {
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/* Use maximum number of line buffers in command mode */
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num_line_buffers = 2;
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}
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/* LINE_BUFFER */
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REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
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}
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static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
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int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
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int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
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bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
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bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
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u32 r;
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r = dsi_read_reg(dsidev, DSI_CTRL);
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r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
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r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
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r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
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r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
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r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
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r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
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r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
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dsi_write_reg(dsidev, DSI_CTRL, r);
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}
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static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
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int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
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int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
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int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
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u32 r;
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/*
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* 0 = TX FIFO packets sent or LPS in corresponding blanking periods
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* 1 = Long blanking packets are sent in corresponding blanking periods
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*/
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r = dsi_read_reg(dsidev, DSI_CTRL);
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r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
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r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
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r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
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r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
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dsi_write_reg(dsidev, DSI_CTRL, r);
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}
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static int dsi_proto_config(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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@ -3725,7 +3807,6 @@ static int dsi_proto_config(struct omap_dss_device *dssdev)
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r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
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r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
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r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
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r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
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r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
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r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
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if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
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@ -3736,6 +3817,13 @@ static int dsi_proto_config(struct omap_dss_device *dssdev)
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dsi_write_reg(dsidev, DSI_CTRL, r);
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dsi_config_vp_num_line_buffers(dssdev);
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
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dsi_config_vp_sync_events(dssdev);
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dsi_config_blanking_modes(dssdev);
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}
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dsi_vc_initial_config(dsidev, 0);
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dsi_vc_initial_config(dsidev, 1);
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dsi_vc_initial_config(dsidev, 2);
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@ -3754,6 +3842,7 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
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unsigned ddr_clk_pre, ddr_clk_post;
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unsigned enter_hs_mode_lat, exit_hs_mode_lat;
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unsigned ths_eot;
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int ndl = dsi_get_num_data_lanes_dssdev(dssdev);
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u32 r;
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r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
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@ -3776,7 +3865,7 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
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/* min 60ns + 52*UI */
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tclk_post = ns2ddr(dsidev, 60) + 26;
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ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
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ths_eot = DIV_ROUND_UP(4, ndl);
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ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
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4);
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@ -3806,8 +3895,115 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
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DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
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enter_hs_mode_lat, exit_hs_mode_lat);
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
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/* TODO: Implement a video mode check_timings function */
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int hsa = dssdev->panel.dsi_vm_data.hsa;
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int hfp = dssdev->panel.dsi_vm_data.hfp;
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int hbp = dssdev->panel.dsi_vm_data.hbp;
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int vsa = dssdev->panel.dsi_vm_data.vsa;
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int vfp = dssdev->panel.dsi_vm_data.vfp;
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int vbp = dssdev->panel.dsi_vm_data.vbp;
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int window_sync = dssdev->panel.dsi_vm_data.window_sync;
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bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
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struct omap_video_timings *timings = &dssdev->panel.timings;
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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int tl, t_he, width_bytes;
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t_he = hsync_end ?
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((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
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width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
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/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
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tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
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DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
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DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
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hfp, hsync_end ? hsa : 0, tl);
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DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
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vsa, timings->y_res);
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r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
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r = FLD_MOD(r, hbp, 11, 0); /* HBP */
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r = FLD_MOD(r, hfp, 23, 12); /* HFP */
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r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
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dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
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r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
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r = FLD_MOD(r, vbp, 7, 0); /* VBP */
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r = FLD_MOD(r, vfp, 15, 8); /* VFP */
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r = FLD_MOD(r, vsa, 23, 16); /* VSA */
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r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
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dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
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r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
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r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
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r = FLD_MOD(r, tl, 31, 16); /* TL */
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dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
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}
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}
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int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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u8 data_type;
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u16 word_count;
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switch (dssdev->panel.dsi_pix_fmt) {
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case OMAP_DSS_DSI_FMT_RGB888:
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data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
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break;
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case OMAP_DSS_DSI_FMT_RGB666:
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data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
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break;
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case OMAP_DSS_DSI_FMT_RGB666_PACKED:
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data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
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break;
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case OMAP_DSS_DSI_FMT_RGB565:
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data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
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break;
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default:
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BUG();
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};
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dsi_if_enable(dsidev, false);
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dsi_vc_enable(dsidev, channel, false);
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/* MODE, 1 = video mode */
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REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
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word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
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dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);
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dsi_vc_enable(dsidev, channel, true);
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dsi_if_enable(dsidev, true);
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dssdev->manager->enable(dssdev->manager);
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return 0;
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}
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EXPORT_SYMBOL(dsi_video_mode_enable);
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void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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dsi_if_enable(dsidev, false);
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dsi_vc_enable(dsidev, channel, false);
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/* MODE, 0 = command mode */
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REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
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dsi_vc_enable(dsidev, channel, true);
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dsi_if_enable(dsidev, true);
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dssdev->manager->disable(dssdev->manager);
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}
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EXPORT_SYMBOL(dsi_video_mode_disable);
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static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
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u16 x, u16 y, u16 w, u16 h)
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{
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@ -4019,28 +4215,9 @@ EXPORT_SYMBOL(omap_dsi_update);
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static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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{
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int r;
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u32 irq;
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irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
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DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
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r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev,
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irq);
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if (r) {
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DSSERR("can't get FRAMEDONE irq\n");
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return r;
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}
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dispc_mgr_set_lcd_display_type(dssdev->manager->id,
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OMAP_DSS_LCD_DISPLAY_TFT);
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dispc_mgr_enable_stallmode(dssdev->manager->id, true);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
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dispc_mgr_set_tft_data_lines(dssdev->manager->id,
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dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
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{
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
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u32 irq;
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struct omap_video_timings timings = {
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.hsw = 1,
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.hfp = 1,
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@ -4050,21 +4227,46 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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.vbp = 0,
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};
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irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
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DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
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r = omap_dispc_register_isr(dsi_framedone_irq_callback,
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(void *) dssdev, irq);
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if (r) {
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DSSERR("can't get FRAMEDONE irq\n");
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return r;
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}
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dispc_mgr_enable_stallmode(dssdev->manager->id, true);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
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dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
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} else {
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dispc_mgr_enable_stallmode(dssdev->manager->id, false);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
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dispc_mgr_set_lcd_timings(dssdev->manager->id,
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&dssdev->panel.timings);
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}
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dispc_mgr_set_lcd_display_type(dssdev->manager->id,
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OMAP_DSS_LCD_DISPLAY_TFT);
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dispc_mgr_set_tft_data_lines(dssdev->manager->id,
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dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
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return 0;
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}
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static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
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{
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u32 irq;
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
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u32 irq;
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irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
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DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
|
||||
irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
|
||||
DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
|
||||
|
||||
omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev,
|
||||
irq);
|
||||
omap_dispc_unregister_isr(dsi_framedone_irq_callback,
|
||||
(void *) dssdev, irq);
|
||||
}
|
||||
}
|
||||
|
||||
static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
|
||||
|
|
|
|||
|
|
@ -228,6 +228,35 @@ void rfbi_bus_lock(void);
|
|||
void rfbi_bus_unlock(void);
|
||||
|
||||
/* DSI */
|
||||
|
||||
struct omap_dss_dsi_videomode_data {
|
||||
/* DSI video mode blanking data */
|
||||
/* Unit: byte clock cycles */
|
||||
u16 hsa;
|
||||
u16 hfp;
|
||||
u16 hbp;
|
||||
/* Unit: line clocks */
|
||||
u16 vsa;
|
||||
u16 vfp;
|
||||
u16 vbp;
|
||||
|
||||
/* DSI blanking modes */
|
||||
int blanking_mode;
|
||||
int hsa_blanking_mode;
|
||||
int hbp_blanking_mode;
|
||||
int hfp_blanking_mode;
|
||||
|
||||
/* Video port sync events */
|
||||
int vp_de_pol;
|
||||
int vp_hsync_pol;
|
||||
int vp_vsync_pol;
|
||||
bool vp_vsync_end;
|
||||
bool vp_hsync_end;
|
||||
|
||||
bool ddr_clk_always_on;
|
||||
int window_sync;
|
||||
};
|
||||
|
||||
void dsi_bus_lock(struct omap_dss_device *dssdev);
|
||||
void dsi_bus_unlock(struct omap_dss_device *dssdev);
|
||||
int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
|
||||
|
|
@ -258,6 +287,8 @@ int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
|
|||
u16 len);
|
||||
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
|
||||
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
|
||||
int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel);
|
||||
void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel);
|
||||
|
||||
/* Board specific data */
|
||||
struct omap_dss_board_info {
|
||||
|
|
@ -505,6 +536,7 @@ struct omap_dss_device {
|
|||
|
||||
enum omap_dss_dsi_pixel_format dsi_pix_fmt;
|
||||
enum omap_dss_dsi_mode dsi_mode;
|
||||
struct omap_dss_dsi_videomode_data dsi_vm_data;
|
||||
} panel;
|
||||
|
||||
struct {
|
||||
|
|
|
|||
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