Merge master.kernel.org:/home/rmk/linux-2.6-arm
This commit is contained in:
Linus Torvalds
Коммит
8b22c249e7
|
|
@ -2,6 +2,8 @@
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* linux/arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
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||||
|
|
@ -165,6 +167,48 @@ __mmap_switched:
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stmia r6, {r0, r4} @ Save control register values
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b start_kernel
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#if defined(CONFIG_SMP)
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.type secondary_startup, #function
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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beq __error
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/*
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* Use the page tables supplied from __cpu_up.
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*/
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adr r4, __secondary_data
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ldmia r4, {r5, r6, r13} @ address to jump to after
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sub r4, r4, r5 @ mmu has been enabled
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ldr r4, [r6, r4] @ get secondary_data.pgdir
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adr lr, __enable_mmu @ return address
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add pc, r10, #12 @ initialise processor
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@ (return control reg)
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/*
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* r6 = &secondary_data
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*/
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ENTRY(__secondary_switched)
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ldr sp, [r6, #4] @ get secondary_data.stack
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mov fp, #0
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b secondary_start_kernel
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.type __secondary_data, %object
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__secondary_data:
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.long .
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.long secondary_data
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.long __secondary_switched
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#endif /* defined(CONFIG_SMP) */
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/*
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|
|
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@ -328,7 +328,7 @@ static void __init setup_processor(void)
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* cpu_init dumps the cache information, initialises SMP specific
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* information, and sets up the per-CPU stacks.
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*/
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void __init cpu_init(void)
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void cpu_init(void)
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{
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unsigned int cpu = smp_processor_id();
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struct stack *stk = &stacks[cpu];
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|
|
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@ -24,6 +24,9 @@
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#include <asm/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/tlbflush.h>
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#include <asm/ptrace.h>
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@ -36,6 +39,13 @@
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cpumask_t cpu_present_mask;
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cpumask_t cpu_online_map;
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/*
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* as from 2.5, kernels no longer have an init_tasks structure
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* so we need some other way of telling a new secondary core
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* where to place its SVC stack
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*/
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struct secondary_data secondary_data;
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/*
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* structures for inter-processor calls
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* - A collection of single bit ipi messages.
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@ -71,6 +81,8 @@ static DEFINE_SPINLOCK(smp_call_function_lock);
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int __init __cpu_up(unsigned int cpu)
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{
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struct task_struct *idle;
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pgd_t *pgd;
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pmd_t *pmd;
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int ret;
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/*
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@ -83,10 +95,55 @@ int __init __cpu_up(unsigned int cpu)
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return PTR_ERR(idle);
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}
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/*
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* Allocate initial page tables to allow the new CPU to
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* enable the MMU safely. This essentially means a set
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* of our "standard" page tables, with the addition of
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* a 1:1 mapping for the physical address of the kernel.
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*/
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pgd = pgd_alloc(&init_mm);
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pmd = pmd_offset(pgd, PHYS_OFFSET);
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*pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |
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PMD_TYPE_SECT | PMD_SECT_AP_WRITE);
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/*
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* We need to tell the secondary core where to find
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* its stack and the page tables.
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*/
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secondary_data.stack = (void *)idle->thread_info + THREAD_SIZE - 8;
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secondary_data.pgdir = virt_to_phys(pgd);
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wmb();
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/*
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* Now bring the CPU into our world.
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*/
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ret = boot_secondary(cpu, idle);
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if (ret == 0) {
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unsigned long timeout;
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/*
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* CPU was successfully started, wait for it
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* to come online or time out.
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*/
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timeout = jiffies + HZ;
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while (time_before(jiffies, timeout)) {
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if (cpu_online(cpu))
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break;
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udelay(10);
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barrier();
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}
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if (!cpu_online(cpu))
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ret = -EIO;
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}
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secondary_data.stack = 0;
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secondary_data.pgdir = 0;
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*pmd_offset(pgd, PHYS_OFFSET) = __pmd(0);
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pgd_free(pgd);
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if (ret) {
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printk(KERN_CRIT "cpu_up: processor %d failed to boot\n", cpu);
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/*
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@ -97,6 +154,56 @@ int __init __cpu_up(unsigned int cpu)
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return ret;
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}
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/*
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* This is the secondary CPU boot entry. We're using this CPUs
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* idle thread stack, but a set of temporary page tables.
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*/
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asmlinkage void __init secondary_start_kernel(void)
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{
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struct mm_struct *mm = &init_mm;
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unsigned int cpu = smp_processor_id();
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printk("CPU%u: Booted secondary processor\n", cpu);
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/*
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* All kernel threads share the same mm context; grab a
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* reference and switch to it.
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*/
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atomic_inc(&mm->mm_users);
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atomic_inc(&mm->mm_count);
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current->active_mm = mm;
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cpu_set(cpu, mm->cpu_vm_mask);
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cpu_switch_mm(mm->pgd, mm);
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enter_lazy_tlb(mm, current);
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cpu_init();
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/*
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* Give the platform a chance to do its own initialisation.
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*/
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platform_secondary_init(cpu);
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/*
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* Enable local interrupts.
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*/
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local_irq_enable();
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local_fiq_enable();
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calibrate_delay();
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smp_store_cpu_info(cpu);
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/*
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* OK, now it's safe to let the boot CPU continue
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*/
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cpu_set(cpu, cpu_online_map);
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/*
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* OK, it's off to the idle thread for us
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*/
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cpu_idle();
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}
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/*
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* Called by both boot and secondaries to move global data into
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* per-processor storage.
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|
|
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@ -12,3 +12,4 @@ obj-$(CONFIG_LEDS) += leds.o
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obj-$(CONFIG_PCI) += pci_v3.o pci.o
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obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o
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obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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|
|
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@ -14,6 +14,7 @@
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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@ -221,7 +222,24 @@ integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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*/
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timer1->TimerClear = 1;
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timer_tick(regs);
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/*
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* the clock tick routines are only processed on the
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* primary CPU
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*/
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if (hard_smp_processor_id() == 0) {
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nmi_tick();
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timer_tick(regs);
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#ifdef CONFIG_SMP
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smp_send_timer();
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#endif
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}
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#ifdef CONFIG_SMP
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/*
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* this is the ARM equivalent of the APIC timer interrupt
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*/
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update_process_times(user_mode(regs));
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#endif /* CONFIG_SMP */
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write_sequnlock(&xtime_lock);
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|
|
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@ -0,0 +1,37 @@
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/*
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* linux/arch/arm/mach-integrator/headsmp.S
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*
|
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* Copyright (c) 2003 ARM Limited
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
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#include <linux/linkage.h>
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#include <linux/init.h>
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__INIT
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/*
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* Integrator specific entry point for secondary CPUs. This provides
|
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* a "holding pen" into which all secondary cores are held until we're
|
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* ready for them to initialise.
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*/
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ENTRY(integrator_secondary_startup)
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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ldr r6, [r6, r4]
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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|
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/*
|
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* we've been released from the holding pen: secondary_stack
|
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* should now contain the SVC stack for this core
|
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*/
|
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b secondary_startup
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1: .long .
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.long phys_pen_release
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|
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@ -22,6 +22,8 @@
|
|||
*/
|
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#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
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#include <asm/hardware.h>
|
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#include <asm/io.h>
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|
|
@ -85,4 +87,4 @@ static int __init leds_init(void)
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|||
return 0;
|
||||
}
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||||
|
||||
__initcall(leds_init);
|
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core_initcall(leds_init);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-cintegrator/platsmp.c
|
||||
*
|
||||
* Copyright (C) 2002 ARM Ltd.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/delay.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/smp.h>
|
||||
|
||||
extern void integrator_secondary_startup(void);
|
||||
|
||||
/*
|
||||
* control for which core is the next to come out of the secondary
|
||||
* boot "holding pen"
|
||||
*/
|
||||
volatile int __initdata pen_release = -1;
|
||||
unsigned long __initdata phys_pen_release = 0;
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
void __init platform_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* the primary core may have used a "cross call" soft interrupt
|
||||
* to get this processor out of WFI in the BootMonitor - make
|
||||
* sure that we are no longer being sent this soft interrupt
|
||||
*/
|
||||
smp_cross_call_done(cpumask_of_cpu(cpu));
|
||||
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
secondary_scan_irqs();
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
*/
|
||||
pen_release = -1;
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
int __init boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/*
|
||||
* set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/*
|
||||
* The secondary processor is waiting to be released from
|
||||
* the holding pen - release it, then wait for it to flag
|
||||
* that it has been released by resetting pen_release.
|
||||
*
|
||||
* Note that "pen_release" is the hardware CPU ID, whereas
|
||||
* "cpu" is Linux's internal ID.
|
||||
*/
|
||||
pen_release = cpu;
|
||||
|
||||
/*
|
||||
* XXX
|
||||
*
|
||||
* This is a later addition to the booting protocol: the
|
||||
* bootMonitor now puts secondary cores into WFI, so
|
||||
* poke_milo() no longer gets the cores moving; we need
|
||||
* to send a soft interrupt to wake the secondary core.
|
||||
* Use smp_cross_call() for this, since there's little
|
||||
* point duplicating the code here
|
||||
*/
|
||||
smp_cross_call(cpumask_of_cpu(cpu));
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return pen_release != -1 ? -ENOSYS : 0;
|
||||
}
|
||||
|
||||
static void __init poke_milo(void)
|
||||
{
|
||||
extern void secondary_startup(void);
|
||||
|
||||
/* nobody is to be released from the pen yet */
|
||||
pen_release = -1;
|
||||
|
||||
phys_pen_release = virt_to_phys(&pen_release);
|
||||
|
||||
/*
|
||||
* write the address of secondary startup into the system-wide
|
||||
* flags register, then clear the bottom two bits, which is what
|
||||
* BootMonitor is waiting for
|
||||
*/
|
||||
#if 1
|
||||
#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
|
||||
__raw_writel(virt_to_phys(integrator_secondary_startup),
|
||||
(IO_ADDRESS(INTEGRATOR_HDR_BASE) +
|
||||
CINTEGRATOR_HDR_FLAGSS_OFFSET));
|
||||
#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
|
||||
__raw_writel(3,
|
||||
(IO_ADDRESS(INTEGRATOR_HDR_BASE) +
|
||||
CINTEGRATOR_HDR_FLAGSC_OFFSET));
|
||||
#endif
|
||||
|
||||
mb();
|
||||
}
|
||||
|
||||
void __init smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
unsigned int ncores = get_core_count();
|
||||
unsigned int cpu = smp_processor_id();
|
||||
int i;
|
||||
|
||||
/* sanity check */
|
||||
if (ncores == 0) {
|
||||
printk(KERN_ERR
|
||||
"Integrator/CP: strange CM count of 0? Default to 1\n");
|
||||
|
||||
ncores = 1;
|
||||
}
|
||||
|
||||
if (ncores > NR_CPUS) {
|
||||
printk(KERN_WARNING
|
||||
"Integrator/CP: no. of cores (%d) greater than configured "
|
||||
"maximum of %d - clipping\n",
|
||||
ncores, NR_CPUS);
|
||||
ncores = NR_CPUS;
|
||||
}
|
||||
|
||||
/*
|
||||
* start with some more config for the Boot CPU, now that
|
||||
* the world is a bit more alive (which was not the case
|
||||
* when smp_prepare_boot_cpu() was called)
|
||||
*/
|
||||
smp_store_cpu_info(cpu);
|
||||
|
||||
/*
|
||||
* are we trying to boot more cores than exist?
|
||||
*/
|
||||
if (max_cpus > ncores)
|
||||
max_cpus = ncores;
|
||||
|
||||
/*
|
||||
* Initialise the present mask - this tells us which CPUs should
|
||||
* be present.
|
||||
*/
|
||||
for (i = 0; i < max_cpus; i++) {
|
||||
cpu_set(i, cpu_present_mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do we need any more CPUs? If so, then let them know where
|
||||
* to start. Note that, on modern versions of MILO, the "poke"
|
||||
* doesn't actually do anything until each individual core is
|
||||
* sent a soft interrupt to get it out of WFI
|
||||
*/
|
||||
if (max_cpus > 1)
|
||||
poke_milo();
|
||||
}
|
||||
|
|
@ -133,6 +133,8 @@ static int pxa_pm_enter(suspend_state_t state)
|
|||
/* *** go zzz *** */
|
||||
pxa_cpu_pm_enter(state);
|
||||
|
||||
cpu_init();
|
||||
|
||||
/* after sleeping, validate the checksum */
|
||||
checksum = 0;
|
||||
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@ static int sa11x0_pm_enter(suspend_state_t state)
|
|||
/* go zzz */
|
||||
sa1100_cpu_suspend();
|
||||
|
||||
cpu_init();
|
||||
|
||||
/*
|
||||
* Ensure not to come back here if it wasn't intended
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
#ifndef ASMARM_ARCH_SMP_H
|
||||
#define ASMARM_ARCH_SMP_H
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define hard_smp_processor_id() \
|
||||
({ \
|
||||
unsigned int cpunum; \
|
||||
__asm__("mrc p15, 0, %0, c0, c0, 5" \
|
||||
: "=r" (cpunum)); \
|
||||
cpunum &= 0x0F; \
|
||||
})
|
||||
|
||||
extern void secondary_scan_irqs(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -55,4 +55,18 @@ extern void smp_cross_call(cpumask_t callmap);
|
|||
*/
|
||||
extern int boot_secondary(unsigned int cpu, struct task_struct *);
|
||||
|
||||
/*
|
||||
* Perform platform specific initialisation of the specified CPU.
|
||||
*/
|
||||
extern void platform_secondary_init(unsigned int cpu);
|
||||
|
||||
/*
|
||||
* Initial data for bringing up a secondary CPU.
|
||||
*/
|
||||
struct secondary_data {
|
||||
unsigned long pgdir;
|
||||
void *stack;
|
||||
};
|
||||
extern struct secondary_data secondary_data;
|
||||
|
||||
#endif /* ifndef __ASM_ARM_SMP_H */
|
||||
|
|
|
|||
|
|
@ -104,6 +104,7 @@ extern void show_pte(struct mm_struct *mm, unsigned long addr);
|
|||
extern void __show_regs(struct pt_regs *);
|
||||
|
||||
extern int cpu_architecture(void);
|
||||
extern void cpu_init(void);
|
||||
|
||||
#define set_cr(x) \
|
||||
__asm__ __volatile__( \
|
||||
|
|
|
|||
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