ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0
This avoids unnecessary instructions for CPUs which implement the IFAR (instruction fault address register). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -45,7 +45,7 @@
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.endm
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.macro pabt_helper
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mov r0, r4 @ pass address of aborted instruction.
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@ PABORT handler takes fault address in r4
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#ifdef MULTI_PABORT
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ldr ip, .LCprocfns
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mov lr, pc
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@ -4,7 +4,7 @@
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/*
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* Function: legacy_pabort
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*
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* Params : r0 = address of aborted instruction
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* Params : r4 = address of aborted instruction
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*
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* Returns : r0 = address of abort
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* : r1 = Simulated IFSR with section translation fault status
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@ -14,6 +14,7 @@
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.align 5
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ENTRY(legacy_pabort)
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mov r0, r4
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mov r1, #5
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mov pc, lr
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ENDPROC(legacy_pabort)
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@ -4,7 +4,7 @@
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/*
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* Function: v6_pabort
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*
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* Params : r0 = address of aborted instruction
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* Params : r4 = address of aborted instruction
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*
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* Returns : r0 = address of abort
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* : r1 = IFSR
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@ -14,6 +14,7 @@
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.align 5
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ENTRY(v6_pabort)
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mov r0, r4
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mrc p15, 0, r1, c5, c0, 1 @ get IFSR
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mov pc, lr
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ENDPROC(v6_pabort)
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@ -4,7 +4,7 @@
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/*
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* Function: v6_pabort
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*
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* Params : r0 = address of aborted instruction
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* Params : r4 = address of aborted instruction
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*
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* Returns : r0 = address of abort
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* : r1 = IFSR
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