zs: move to the serial subsystem
This is a reimplementation of the zs driver for the serial subsystem. Any resemblance to the old driver is purely coincidential. ;-) I do hope I got the handling of modem lines right -- better do not tackle me about the issue unless you feel too good... Any users of the old driver: please note the numbers of the serial lines have now been swapped, i.e. ttyS0 <-> ttyS1 and ttyS2 <-> ttyS3. It has to do with the modem lines mentioned above; basically the port A in a given chip has to be initialised before the port B if you want to use the latter as the serial console (which is usually the case), as operations on modem lines of the serial line associated with the port B access both ports (see the comment at the top of the driver for the details of wiring used). Please update your scripts. This is also the reason each SCC now requests an IRQ once only (as seen in "/proc/interrupts") -- the handler takes care of both ports at once as the line associated with the port B has to take status update interrupts from both ports (and yet the line of the port A takes its own for itself too). The old driver never got it right... Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Maciej W. Rozycki
Linus Torvalds
Родитель
b187f180cc
Коммит
8b4a40809e
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@ -4110,6 +4110,11 @@ W: http://www.polyware.nl/~middelin/En/hobbies.html
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W: http://www.polyware.nl/~middelin/hobbies.html
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S: Maintained
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ZS DECSTATION Z85C30 SERIAL DRIVER
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P: Maciej W. Rozycki
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M: macro@linux-mips.org
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S: Maintained
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THE REST
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P: Linus Torvalds
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S: Buried alive in reporters
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@ -372,39 +372,6 @@ config ISTALLION
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To compile this driver as a module, choose M here: the
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module will be called istallion.
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config SERIAL_DEC
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bool "DECstation serial support"
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depends on MACH_DECSTATION
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default y
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help
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This selects whether you want to be asked about drivers for
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DECstation serial ports.
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Note that the answer to this question won't directly affect the
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kernel: saying N will just cause the configurator to skip all
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the questions about DECstation serial ports.
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config SERIAL_DEC_CONSOLE
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bool "Support for console on a DECstation serial port"
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depends on SERIAL_DEC
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default y
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help
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If you say Y here, it will be possible to use a serial port as the
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system console (the system console is the device which receives all
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kernel messages and warnings and which allows logins in single user
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mode). Note that the firmware uses ttyS0 as the serial console on
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the Maxine and ttyS2 on the others.
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If unsure, say Y.
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config ZS
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bool "Z85C30 Serial Support"
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depends on SERIAL_DEC
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default y
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help
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Documentation on the Zilog 85C350 serial communications controller
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is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>
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config A2232
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tristate "Commodore A2232 serial support (EXPERIMENTAL)"
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depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
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@ -1,67 +0,0 @@
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/*
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* sercons.c
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* choose the right serial device at boot time
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*
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* triemer 6-SEP-1998
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* sercons.c is designed to allow the three different kinds
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* of serial devices under the decstation world to co-exist
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* in the same kernel. The idea here is to abstract
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* the pieces of the drivers that are common to this file
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* so that they do not clash at compile time and runtime.
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*
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* HK 16-SEP-1998 v0.002
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* removed the PROM console as this is not a real serial
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* device. Added support for PROM console in drivers/char/tty_io.c
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* instead. Although it may work to enable more than one
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* console device I strongly recommend to use only one.
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*/
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#include <linux/init.h>
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#include <asm/dec/machtype.h>
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#ifdef CONFIG_ZS
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extern int zs_init(void);
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#endif
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#ifdef CONFIG_SERIAL_CONSOLE
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#ifdef CONFIG_ZS
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extern void zs_serial_console_init(void);
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#endif
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#endif
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/* rs_init - starts up the serial interface -
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handle normal case of starting up the serial interface */
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#ifdef CONFIG_SERIAL
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int __init rs_init(void)
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{
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#ifdef CONFIG_ZS
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if (IOASIC)
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return zs_init();
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#endif
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return -ENXIO;
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}
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__initcall(rs_init);
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#endif
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#ifdef CONFIG_SERIAL_CONSOLE
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/* serial_console_init handles the special case of starting
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* up the console on the serial port
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*/
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static int __init decserial_console_init(void)
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{
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#ifdef CONFIG_ZS
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if (IOASIC)
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zs_serial_console_init();
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#endif
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return 0;
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}
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console_initcall(decserial_console_init);
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#endif
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@ -486,6 +486,36 @@ config SERIAL_DZ_CONSOLE
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If unsure, say Y.
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config SERIAL_ZS
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tristate "DECstation Z85C30 serial support"
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depends on MACH_DECSTATION
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select SERIAL_CORE
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default y
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---help---
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Support for the Zilog 85C350 serial communications controller used
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for serial ports in newer DECstation systems. These include the
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DECsystem 5900 and all models of the DECstation and DECsystem 5000
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systems except from model 200.
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If unsure, say Y. To compile this driver as a module, choose M here:
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the module will be called zs.
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config SERIAL_ZS_CONSOLE
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bool "Support for console on a DECstation Z85C30 serial port"
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depends on SERIAL_ZS=y
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select SERIAL_CORE_CONSOLE
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default y
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---help---
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If you say Y here, it will be possible to use a serial port as the
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system console (the system console is the device which receives all
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kernel messages and warnings and which allows logins in single user
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mode).
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Note that the firmware uses ttyS1 as the serial console on the
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Maxine and ttyS3 on the others using this driver.
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If unsure, say Y.
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config SERIAL_21285
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tristate "DC21285 serial port support"
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depends on ARM && FOOTBRIDGE
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@ -43,6 +43,7 @@ obj-$(CONFIG_V850E_UART) += v850e_uart.o
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obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
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obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
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obj-$(CONFIG_SERIAL_DZ) += dz.o
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obj-$(CONFIG_SERIAL_ZS) += zs.o
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obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
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obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
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obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,284 @@
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/*
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* zs.h: Definitions for the DECstation Z85C30 serial driver.
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*
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* Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
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* Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
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*
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* Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 2004, 2005, 2007 Maciej W. Rozycki
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*/
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#ifndef _SERIAL_ZS_H
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#define _SERIAL_ZS_H
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#ifdef __KERNEL__
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#define ZS_NUM_REGS 16
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/*
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* This is our internal structure for each serial port's state.
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*/
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struct zs_port {
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struct zs_scc *scc; /* Containing SCC. */
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struct uart_port port; /* Underlying UART. */
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int clk_mode; /* May be 1, 16, 32, or 64. */
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unsigned int tty_break; /* Set on BREAK condition. */
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int tx_stopped; /* Output is suspended. */
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unsigned int mctrl; /* State of modem lines. */
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u8 brk; /* BREAK state from RR0. */
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u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
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};
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/*
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* Per-SCC state for locking and the interrupt handler.
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*/
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struct zs_scc {
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struct zs_port zport[2];
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spinlock_t zlock;
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atomic_t irq_guard;
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int initialised;
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};
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#endif /* __KERNEL__ */
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/*
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* Conversion routines to/from brg time constants from/to bits per second.
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*/
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#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
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#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
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/*
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* The Zilog register set.
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*/
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/* Write Register 0 (Command) */
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#define R0 0 /* Register selects */
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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#define NULLCODE 0 /* Null Code */
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#define POINT_HIGH 0x8 /* Select upper half of registers */
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#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
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#define SEND_ABORT 0x18 /* HDLC Abort */
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#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
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#define RES_Tx_P 0x28 /* Reset TxINT Pending */
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#define ERR_RES 0x30 /* Error Reset */
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#define RES_H_IUS 0x38 /* Reset highest IUS */
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#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
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#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
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#define RES_EOM_L 0xC0 /* Reset EOM latch */
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/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
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#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
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#define TxINT_ENAB 0x2 /* Tx Int Enable */
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#define PAR_SPEC 0x4 /* Parity is special condition */
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#define RxINT_DISAB 0 /* Rx Int Disable */
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#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
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#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
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#define RxINT_ERR 0x18 /* Int on error only */
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#define RxINT_MASK 0x18
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#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
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#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
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#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
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/* Write Register 2 (Interrupt Vector) */
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/* Write Register 3 (Receive Parameters and Control) */
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#define RxENABLE 0x1 /* Rx Enable */
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#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
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#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
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#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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#define ENT_HM 0x10 /* Enter Hunt Mode */
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#define AUTO_ENAB 0x20 /* Auto Enables */
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#define Rx5 0x0 /* Rx 5 Bits/Character */
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#define Rx7 0x40 /* Rx 7 Bits/Character */
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#define Rx6 0x80 /* Rx 6 Bits/Character */
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#define Rx8 0xc0 /* Rx 8 Bits/Character */
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#define RxNBITS_MASK 0xc0
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/* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
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#define PAR_ENA 0x1 /* Parity Enable */
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#define PAR_EVEN 0x2 /* Parity Even/Odd* */
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#define SYNC_ENAB 0 /* Sync Modes Enable */
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#define SB1 0x4 /* 1 stop bit/char */
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#define SB15 0x8 /* 1.5 stop bits/char */
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#define SB2 0xc /* 2 stop bits/char */
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#define SB_MASK 0xc
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#define MONSYNC 0 /* 8 Bit Sync character */
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#define BISYNC 0x10 /* 16 bit sync character */
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#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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#define EXTSYNC 0x30 /* External Sync Mode */
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#define X1CLK 0x0 /* x1 clock mode */
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#define X16CLK 0x40 /* x16 clock mode */
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#define X32CLK 0x80 /* x32 clock mode */
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#define X64CLK 0xc0 /* x64 clock mode */
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#define XCLK_MASK 0xc0
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/* Write Register 5 (Transmit Parameters and Controls) */
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#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
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#define RTS 0x2 /* RTS */
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#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
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#define TxENAB 0x8 /* Tx Enable */
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#define SND_BRK 0x10 /* Send Break */
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#define Tx5 0x0 /* Tx 5 bits (or less)/character */
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#define Tx7 0x20 /* Tx 7 bits/character */
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#define Tx6 0x40 /* Tx 6 bits/character */
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#define Tx8 0x60 /* Tx 8 bits/character */
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#define TxNBITS_MASK 0x60
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#define DTR 0x80 /* DTR */
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/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
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/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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/* Write Register 8 (Transmit Buffer) */
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/* Write Register 9 (Master Interrupt Control) */
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#define VIS 1 /* Vector Includes Status */
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#define NV 2 /* No Vector */
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#define DLC 4 /* Disable Lower Chain */
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#define MIE 8 /* Master Interrupt Enable */
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#define STATHI 0x10 /* Status high */
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#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
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#define NORESET 0 /* No reset on write to R9 */
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#define CHRB 0x40 /* Reset channel B */
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#define CHRA 0x80 /* Reset channel A */
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#define FHWRES 0xc0 /* Force hardware reset */
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/* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
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#define BIT6 1 /* 6 bit/8bit sync */
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#define LOOPMODE 2 /* SDLC Loop mode */
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#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
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#define MARKIDLE 8 /* Mark/flag on idle */
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#define GAOP 0x10 /* Go active on poll */
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#define NRZ 0 /* NRZ mode */
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#define NRZI 0x20 /* NRZI mode */
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#define FM1 0x40 /* FM1 (transition = 1) */
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#define FM0 0x60 /* FM0 (transition = 0) */
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#define CRCPS 0x80 /* CRC Preset I/O */
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/* Write Register 11 (Clock Mode Control) */
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#define TRxCXT 0 /* TRxC = Xtal output */
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#define TRxCTC 1 /* TRxC = Transmit clock */
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#define TRxCBR 2 /* TRxC = BR Generator Output */
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#define TRxCDP 3 /* TRxC = DPLL output */
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#define TRxCOI 4 /* TRxC O/I */
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#define TCRTxCP 0 /* Transmit clock = RTxC pin */
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#define TCTRxCP 8 /* Transmit clock = TRxC pin */
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#define TCBR 0x10 /* Transmit clock = BR Generator output */
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#define TCDPLL 0x18 /* Transmit clock = DPLL output */
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#define RCRTxCP 0 /* Receive clock = RTxC pin */
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#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
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#define RCBR 0x40 /* Receive clock = BR Generator output */
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#define RCDPLL 0x60 /* Receive clock = DPLL output */
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#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
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/* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
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/* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
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/* Write Register 14 (Miscellaneous Control Bits) */
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#define BRENABL 1 /* Baud rate generator enable */
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#define BRSRC 2 /* Baud rate generator source */
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#define DTRREQ 4 /* DTR/Request function */
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#define AUTOECHO 8 /* Auto Echo */
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#define LOOPBAK 0x10 /* Local loopback */
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#define SEARCH 0x20 /* Enter search mode */
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#define RMC 0x40 /* Reset missing clock */
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#define DISDPLL 0x60 /* Disable DPLL */
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#define SSBR 0x80 /* Set DPLL source = BR generator */
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#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
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#define SFMM 0xc0 /* Set FM mode */
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#define SNRZI 0xe0 /* Set NRZI mode */
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/* Write Register 15 (External/Status Interrupt Control) */
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#define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
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#define ZCIE 2 /* Zero count IE */
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#define DCDIE 8 /* DCD IE */
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#define SYNCIE 0x10 /* Sync/hunt IE */
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#define CTSIE 0x20 /* CTS IE */
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#define TxUIE 0x40 /* Tx Underrun/EOM IE */
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#define BRKIE 0x80 /* Break/Abort IE */
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/* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
|
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#define Rx_CH_AV 0x1 /* Rx Character Available */
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#define ZCOUNT 0x2 /* Zero count */
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#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
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#define DCD 0x8 /* DCD */
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#define SYNC_HUNT 0x10 /* Sync/hunt */
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#define CTS 0x20 /* CTS */
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#define TxEOM 0x40 /* Tx underrun */
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#define BRK_ABRT 0x80 /* Break/Abort */
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/* Read Register 1 (Special Receive Condition Status) */
|
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#define ALL_SNT 0x1 /* All sent */
|
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/* Residue Data for 8 Rx bits/char programmed */
|
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#define RES3 0x8 /* 0/3 */
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#define RES4 0x4 /* 0/4 */
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#define RES5 0xc /* 0/5 */
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#define RES6 0x2 /* 0/6 */
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#define RES7 0xa /* 0/7 */
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#define RES8 0x6 /* 0/8 */
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#define RES18 0xe /* 1/8 */
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#define RES28 0x0 /* 2/8 */
|
||||
/* Special Rx Condition Interrupts */
|
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#define PAR_ERR 0x10 /* Parity Error */
|
||||
#define Rx_OVR 0x20 /* Rx Overrun Error */
|
||||
#define FRM_ERR 0x40 /* CRC/Framing Error */
|
||||
#define END_FR 0x80 /* End of Frame (SDLC) */
|
||||
|
||||
/* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
|
||||
|
||||
/* Read Register 2 (Modified Interrupt Vector -- channel B). */
|
||||
|
||||
/* Read Register 3 (Interrupt Pending Bits -- channel A only). */
|
||||
#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
|
||||
#define CHBTxIP 0x2 /* Channel B Tx IP */
|
||||
#define CHBRxIP 0x4 /* Channel B Rx IP */
|
||||
#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
|
||||
#define CHATxIP 0x10 /* Channel A Tx IP */
|
||||
#define CHARxIP 0x20 /* Channel A Rx IP */
|
||||
|
||||
/* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
|
||||
|
||||
/* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
|
||||
|
||||
/* Read Register 8 (Receive Data) */
|
||||
|
||||
/* Read Register 10 (Miscellaneous Status Bits) */
|
||||
#define ONLOOP 2 /* On loop */
|
||||
#define LOOPSEND 0x10 /* Loop sending */
|
||||
#define CLK2MIS 0x40 /* Two clocks missing */
|
||||
#define CLK1MIS 0x80 /* One clock missing */
|
||||
|
||||
/* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
|
||||
|
||||
/* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
|
||||
|
||||
/* Read Register 15 (External/Status Interrupt Control (WR15)) */
|
||||
|
||||
#endif /* _SERIAL_ZS_H */
|
||||
|
|
@ -5,7 +5,6 @@
|
|||
# Object file lists.
|
||||
|
||||
obj-$(CONFIG_TC) += tc.o tc-driver.o
|
||||
obj-$(CONFIG_ZS) += zs.o
|
||||
obj-$(CONFIG_VT) += lk201.o lk201-map.o lk201-remap.o
|
||||
|
||||
$(obj)/lk201-map.o: $(obj)/lk201-map.c
|
||||
|
|
|
|||
2203
drivers/tc/zs.c
2203
drivers/tc/zs.c
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
404
drivers/tc/zs.h
404
drivers/tc/zs.h
|
|
@ -1,404 +0,0 @@
|
|||
/*
|
||||
* drivers/tc/zs.h: Definitions for the DECstation Z85C30 serial driver.
|
||||
*
|
||||
* Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
|
||||
* Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
|
||||
*
|
||||
* Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
|
||||
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
|
||||
* Copyright (C) 2004, 2005 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef _DECSERIAL_H
|
||||
#define _DECSERIAL_H
|
||||
|
||||
#include <asm/dec/serial.h>
|
||||
|
||||
#define NUM_ZSREGS 16
|
||||
|
||||
struct serial_struct {
|
||||
int type;
|
||||
int line;
|
||||
int port;
|
||||
int irq;
|
||||
int flags;
|
||||
int xmit_fifo_size;
|
||||
int custom_divisor;
|
||||
int baud_base;
|
||||
unsigned short close_delay;
|
||||
char reserved_char[2];
|
||||
int hub6;
|
||||
unsigned short closing_wait; /* time to wait before closing */
|
||||
unsigned short closing_wait2; /* no longer used... */
|
||||
int reserved[4];
|
||||
};
|
||||
|
||||
/*
|
||||
* For the close wait times, 0 means wait forever for serial port to
|
||||
* flush its output. 65535 means don't wait at all.
|
||||
*/
|
||||
#define ZILOG_CLOSING_WAIT_INF 0
|
||||
#define ZILOG_CLOSING_WAIT_NONE 65535
|
||||
|
||||
/*
|
||||
* Definitions for ZILOG_struct (and serial_struct) flags field
|
||||
*/
|
||||
#define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
|
||||
on the callout port */
|
||||
#define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
|
||||
#define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */
|
||||
#define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
|
||||
|
||||
#define ZILOG_SPD_MASK 0x0030
|
||||
#define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
|
||||
|
||||
#define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
|
||||
#define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */
|
||||
|
||||
#define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
|
||||
#define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
|
||||
#define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
|
||||
#define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
|
||||
#define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
|
||||
|
||||
#define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */
|
||||
#define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged
|
||||
* users can set or reset */
|
||||
|
||||
/* Internal flags used only by kernel/chr_drv/serial.c */
|
||||
#define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
|
||||
#define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
|
||||
#define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
|
||||
#define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
|
||||
#define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
|
||||
#define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
|
||||
#define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
|
||||
|
||||
/* Software state per channel */
|
||||
|
||||
#ifdef __KERNEL__
|
||||
/*
|
||||
* This is our internal structure for each serial port's state.
|
||||
*
|
||||
* Many fields are paralleled by the structure used by the serial_struct
|
||||
* structure.
|
||||
*
|
||||
* For definitions of the flags field, see tty.h
|
||||
*/
|
||||
|
||||
struct dec_zschannel {
|
||||
volatile unsigned char *control;
|
||||
volatile unsigned char *data;
|
||||
|
||||
/* Current write register values */
|
||||
unsigned char curregs[NUM_ZSREGS];
|
||||
};
|
||||
|
||||
struct dec_serial {
|
||||
struct dec_serial *zs_next; /* For IRQ servicing chain. */
|
||||
struct dec_zschannel *zs_channel; /* Channel registers. */
|
||||
struct dec_zschannel *zs_chan_a; /* A side registers. */
|
||||
unsigned char read_reg_zero;
|
||||
|
||||
struct dec_serial_hook *hook; /* Hook on this channel. */
|
||||
int tty_break; /* Set on BREAK condition. */
|
||||
int is_cons; /* Is this our console. */
|
||||
int tx_active; /* Char is being xmitted. */
|
||||
int tx_stopped; /* Output is suspended. */
|
||||
|
||||
/*
|
||||
* We need to know the current clock divisor
|
||||
* to read the bps rate the chip has currently loaded.
|
||||
*/
|
||||
int clk_divisor; /* May be 1, 16, 32, or 64. */
|
||||
int zs_baud;
|
||||
|
||||
char change_needed;
|
||||
|
||||
int magic;
|
||||
int baud_base;
|
||||
int port;
|
||||
int irq;
|
||||
int flags; /* Defined in tty.h. */
|
||||
int type; /* UART type. */
|
||||
struct tty_struct *tty;
|
||||
int read_status_mask;
|
||||
int ignore_status_mask;
|
||||
int timeout;
|
||||
int xmit_fifo_size;
|
||||
int custom_divisor;
|
||||
int x_char; /* XON/XOFF character. */
|
||||
int close_delay;
|
||||
unsigned short closing_wait;
|
||||
unsigned short closing_wait2;
|
||||
unsigned long event;
|
||||
unsigned long last_active;
|
||||
int line;
|
||||
int count; /* # of fds on device. */
|
||||
int blocked_open; /* # of blocked opens. */
|
||||
unsigned char *xmit_buf;
|
||||
int xmit_head;
|
||||
int xmit_tail;
|
||||
int xmit_cnt;
|
||||
struct tasklet_struct tlet;
|
||||
wait_queue_head_t open_wait;
|
||||
wait_queue_head_t close_wait;
|
||||
};
|
||||
|
||||
|
||||
#define SERIAL_MAGIC 0x5301
|
||||
|
||||
/*
|
||||
* The size of the serial xmit buffer is 1 page, or 4096 bytes
|
||||
*/
|
||||
#define SERIAL_XMIT_SIZE 4096
|
||||
|
||||
/*
|
||||
* Events are used to schedule things to happen at timer-interrupt
|
||||
* time, instead of at rs interrupt time.
|
||||
*/
|
||||
#define RS_EVENT_WRITE_WAKEUP 0
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
/* Conversion routines to/from brg time constants from/to bits
|
||||
* per second.
|
||||
*/
|
||||
#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
|
||||
#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
|
||||
|
||||
/* The Zilog register set */
|
||||
|
||||
#define FLAG 0x7e
|
||||
|
||||
/* Write Register 0 */
|
||||
#define R0 0 /* Register selects */
|
||||
#define R1 1
|
||||
#define R2 2
|
||||
#define R3 3
|
||||
#define R4 4
|
||||
#define R5 5
|
||||
#define R6 6
|
||||
#define R7 7
|
||||
#define R8 8
|
||||
#define R9 9
|
||||
#define R10 10
|
||||
#define R11 11
|
||||
#define R12 12
|
||||
#define R13 13
|
||||
#define R14 14
|
||||
#define R15 15
|
||||
|
||||
#define NULLCODE 0 /* Null Code */
|
||||
#define POINT_HIGH 0x8 /* Select upper half of registers */
|
||||
#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
|
||||
#define SEND_ABORT 0x18 /* HDLC Abort */
|
||||
#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
|
||||
#define RES_Tx_P 0x28 /* Reset TxINT Pending */
|
||||
#define ERR_RES 0x30 /* Error Reset */
|
||||
#define RES_H_IUS 0x38 /* Reset highest IUS */
|
||||
|
||||
#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
|
||||
#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
|
||||
#define RES_EOM_L 0xC0 /* Reset EOM latch */
|
||||
|
||||
/* Write Register 1 */
|
||||
|
||||
#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
|
||||
#define TxINT_ENAB 0x2 /* Tx Int Enable */
|
||||
#define PAR_SPEC 0x4 /* Parity is special condition */
|
||||
|
||||
#define RxINT_DISAB 0 /* Rx Int Disable */
|
||||
#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
|
||||
#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
|
||||
#define RxINT_ERR 0x18 /* Int on error only */
|
||||
#define RxINT_MASK 0x18
|
||||
|
||||
#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
|
||||
#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
|
||||
#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
|
||||
|
||||
/* Write Register #2 (Interrupt Vector) */
|
||||
|
||||
/* Write Register 3 */
|
||||
|
||||
#define RxENABLE 0x1 /* Rx Enable */
|
||||
#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
|
||||
#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
|
||||
#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
|
||||
#define ENT_HM 0x10 /* Enter Hunt Mode */
|
||||
#define AUTO_ENAB 0x20 /* Auto Enables */
|
||||
#define Rx5 0x0 /* Rx 5 Bits/Character */
|
||||
#define Rx7 0x40 /* Rx 7 Bits/Character */
|
||||
#define Rx6 0x80 /* Rx 6 Bits/Character */
|
||||
#define Rx8 0xc0 /* Rx 8 Bits/Character */
|
||||
#define RxNBITS_MASK 0xc0
|
||||
|
||||
/* Write Register 4 */
|
||||
|
||||
#define PAR_ENA 0x1 /* Parity Enable */
|
||||
#define PAR_EVEN 0x2 /* Parity Even/Odd* */
|
||||
|
||||
#define SYNC_ENAB 0 /* Sync Modes Enable */
|
||||
#define SB1 0x4 /* 1 stop bit/char */
|
||||
#define SB15 0x8 /* 1.5 stop bits/char */
|
||||
#define SB2 0xc /* 2 stop bits/char */
|
||||
#define SB_MASK 0xc
|
||||
|
||||
#define MONSYNC 0 /* 8 Bit Sync character */
|
||||
#define BISYNC 0x10 /* 16 bit sync character */
|
||||
#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
|
||||
#define EXTSYNC 0x30 /* External Sync Mode */
|
||||
|
||||
#define X1CLK 0x0 /* x1 clock mode */
|
||||
#define X16CLK 0x40 /* x16 clock mode */
|
||||
#define X32CLK 0x80 /* x32 clock mode */
|
||||
#define X64CLK 0xC0 /* x64 clock mode */
|
||||
#define XCLK_MASK 0xC0
|
||||
|
||||
/* Write Register 5 */
|
||||
|
||||
#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
|
||||
#define RTS 0x2 /* RTS */
|
||||
#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
|
||||
#define TxENAB 0x8 /* Tx Enable */
|
||||
#define SND_BRK 0x10 /* Send Break */
|
||||
#define Tx5 0x0 /* Tx 5 bits (or less)/character */
|
||||
#define Tx7 0x20 /* Tx 7 bits/character */
|
||||
#define Tx6 0x40 /* Tx 6 bits/character */
|
||||
#define Tx8 0x60 /* Tx 8 bits/character */
|
||||
#define TxNBITS_MASK 0x60
|
||||
#define DTR 0x80 /* DTR */
|
||||
|
||||
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
|
||||
|
||||
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
|
||||
|
||||
/* Write Register 8 (transmit buffer) */
|
||||
|
||||
/* Write Register 9 (Master interrupt control) */
|
||||
#define VIS 1 /* Vector Includes Status */
|
||||
#define NV 2 /* No Vector */
|
||||
#define DLC 4 /* Disable Lower Chain */
|
||||
#define MIE 8 /* Master Interrupt Enable */
|
||||
#define STATHI 0x10 /* Status high */
|
||||
#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
|
||||
#define NORESET 0 /* No reset on write to R9 */
|
||||
#define CHRB 0x40 /* Reset channel B */
|
||||
#define CHRA 0x80 /* Reset channel A */
|
||||
#define FHWRES 0xc0 /* Force hardware reset */
|
||||
|
||||
/* Write Register 10 (misc control bits) */
|
||||
#define BIT6 1 /* 6 bit/8bit sync */
|
||||
#define LOOPMODE 2 /* SDLC Loop mode */
|
||||
#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
|
||||
#define MARKIDLE 8 /* Mark/flag on idle */
|
||||
#define GAOP 0x10 /* Go active on poll */
|
||||
#define NRZ 0 /* NRZ mode */
|
||||
#define NRZI 0x20 /* NRZI mode */
|
||||
#define FM1 0x40 /* FM1 (transition = 1) */
|
||||
#define FM0 0x60 /* FM0 (transition = 0) */
|
||||
#define CRCPS 0x80 /* CRC Preset I/O */
|
||||
|
||||
/* Write Register 11 (Clock Mode control) */
|
||||
#define TRxCXT 0 /* TRxC = Xtal output */
|
||||
#define TRxCTC 1 /* TRxC = Transmit clock */
|
||||
#define TRxCBR 2 /* TRxC = BR Generator Output */
|
||||
#define TRxCDP 3 /* TRxC = DPLL output */
|
||||
#define TRxCOI 4 /* TRxC O/I */
|
||||
#define TCRTxCP 0 /* Transmit clock = RTxC pin */
|
||||
#define TCTRxCP 8 /* Transmit clock = TRxC pin */
|
||||
#define TCBR 0x10 /* Transmit clock = BR Generator output */
|
||||
#define TCDPLL 0x18 /* Transmit clock = DPLL output */
|
||||
#define RCRTxCP 0 /* Receive clock = RTxC pin */
|
||||
#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
|
||||
#define RCBR 0x40 /* Receive clock = BR Generator output */
|
||||
#define RCDPLL 0x60 /* Receive clock = DPLL output */
|
||||
#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
|
||||
|
||||
/* Write Register 12 (lower byte of baud rate generator time constant) */
|
||||
|
||||
/* Write Register 13 (upper byte of baud rate generator time constant) */
|
||||
|
||||
/* Write Register 14 (Misc control bits) */
|
||||
#define BRENABL 1 /* Baud rate generator enable */
|
||||
#define BRSRC 2 /* Baud rate generator source */
|
||||
#define DTRREQ 4 /* DTR/Request function */
|
||||
#define AUTOECHO 8 /* Auto Echo */
|
||||
#define LOOPBAK 0x10 /* Local loopback */
|
||||
#define SEARCH 0x20 /* Enter search mode */
|
||||
#define RMC 0x40 /* Reset missing clock */
|
||||
#define DISDPLL 0x60 /* Disable DPLL */
|
||||
#define SSBR 0x80 /* Set DPLL source = BR generator */
|
||||
#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
|
||||
#define SFMM 0xc0 /* Set FM mode */
|
||||
#define SNRZI 0xe0 /* Set NRZI mode */
|
||||
|
||||
/* Write Register 15 (external/status interrupt control) */
|
||||
#define ZCIE 2 /* Zero count IE */
|
||||
#define DCDIE 8 /* DCD IE */
|
||||
#define SYNCIE 0x10 /* Sync/hunt IE */
|
||||
#define CTSIE 0x20 /* CTS IE */
|
||||
#define TxUIE 0x40 /* Tx Underrun/EOM IE */
|
||||
#define BRKIE 0x80 /* Break/Abort IE */
|
||||
|
||||
|
||||
/* Read Register 0 */
|
||||
#define Rx_CH_AV 0x1 /* Rx Character Available */
|
||||
#define ZCOUNT 0x2 /* Zero count */
|
||||
#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
|
||||
#define DCD 0x8 /* DCD */
|
||||
#define SYNC_HUNT 0x10 /* Sync/hunt */
|
||||
#define CTS 0x20 /* CTS */
|
||||
#define TxEOM 0x40 /* Tx underrun */
|
||||
#define BRK_ABRT 0x80 /* Break/Abort */
|
||||
|
||||
/* Read Register 1 */
|
||||
#define ALL_SNT 0x1 /* All sent */
|
||||
/* Residue Data for 8 Rx bits/char programmed */
|
||||
#define RES3 0x8 /* 0/3 */
|
||||
#define RES4 0x4 /* 0/4 */
|
||||
#define RES5 0xc /* 0/5 */
|
||||
#define RES6 0x2 /* 0/6 */
|
||||
#define RES7 0xa /* 0/7 */
|
||||
#define RES8 0x6 /* 0/8 */
|
||||
#define RES18 0xe /* 1/8 */
|
||||
#define RES28 0x0 /* 2/8 */
|
||||
/* Special Rx Condition Interrupts */
|
||||
#define PAR_ERR 0x10 /* Parity error */
|
||||
#define Rx_OVR 0x20 /* Rx Overrun Error */
|
||||
#define FRM_ERR 0x40 /* CRC/Framing Error */
|
||||
#define END_FR 0x80 /* End of Frame (SDLC) */
|
||||
|
||||
/* Read Register 2 (channel b only) - Interrupt vector */
|
||||
|
||||
/* Read Register 3 (interrupt pending register) ch a only */
|
||||
#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
|
||||
#define CHBTxIP 0x2 /* Channel B Tx IP */
|
||||
#define CHBRxIP 0x4 /* Channel B Rx IP */
|
||||
#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
|
||||
#define CHATxIP 0x10 /* Channel A Tx IP */
|
||||
#define CHARxIP 0x20 /* Channel A Rx IP */
|
||||
|
||||
/* Read Register 8 (receive data register) */
|
||||
|
||||
/* Read Register 10 (misc status bits) */
|
||||
#define ONLOOP 2 /* On loop */
|
||||
#define LOOPSEND 0x10 /* Loop sending */
|
||||
#define CLK2MIS 0x40 /* Two clocks missing */
|
||||
#define CLK1MIS 0x80 /* One clock missing */
|
||||
|
||||
/* Read Register 12 (lower byte of baud rate generator constant) */
|
||||
|
||||
/* Read Register 13 (upper byte of baud rate generator constant) */
|
||||
|
||||
/* Read Register 15 (value of WR 15) */
|
||||
|
||||
/* Misc macros */
|
||||
#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
|
||||
#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
|
||||
garbage = read_zsdata(channel); \
|
||||
garbage = read_zsdata(channel); \
|
||||
garbage = read_zsdata(channel); \
|
||||
} while(0)
|
||||
|
||||
#endif /* !(_DECSERIAL_H) */
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
/*
|
||||
* include/asm-mips/dec/serial.h
|
||||
*
|
||||
* Definitions common to all DECstation serial devices.
|
||||
*
|
||||
* Copyright (C) 2004 Maciej W. Rozycki
|
||||
*
|
||||
* Based on bits extracted from drivers/tc/zs.h for which
|
||||
* the following copyrights apply:
|
||||
*
|
||||
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
|
||||
* Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
|
||||
* Copyright (C) Harald Koerfgen
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef __ASM_MIPS_DEC_SERIAL_H
|
||||
#define __ASM_MIPS_DEC_SERIAL_H
|
||||
|
||||
struct dec_serial_hook {
|
||||
int (*init_channel)(void *handle);
|
||||
void (*init_info)(void *handle);
|
||||
void (*rx_char)(unsigned char ch, unsigned char fl);
|
||||
int (*poll_rx_char)(void *handle);
|
||||
int (*poll_tx_char)(void *handle, unsigned char ch);
|
||||
unsigned int cflags;
|
||||
};
|
||||
|
||||
extern int register_dec_serial_hook(unsigned int channel,
|
||||
struct dec_serial_hook *hook);
|
||||
extern int unregister_dec_serial_hook(unsigned int channel);
|
||||
|
||||
#endif /* __ASM_MIPS_DEC_SERIAL_H */
|
||||
|
|
@ -62,8 +62,9 @@
|
|||
/* NEC v850. */
|
||||
#define PORT_V850E_UART 40
|
||||
|
||||
/* DZ */
|
||||
#define PORT_DZ 47
|
||||
/* DEC */
|
||||
#define PORT_DZ 46
|
||||
#define PORT_ZS 47
|
||||
|
||||
/* Parisc type numbers. */
|
||||
#define PORT_MUX 48
|
||||
|
|
|
|||
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