Apple SoC DT updates for 6.2 (v2).
This includes: * L1/L2 cache topology for t600x * CPUfreq nodes for t8103/t600x * DT binding for CPUfreq * Associated MAINTAINERS update The CPUfreq driver was already merged for 6.2 via its tree. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSByI3Ki0mXziclZJcd+FPLCI8zYgUCY4wjTAAKCRAd+FPLCI8z YpOSAP9cRxrug+82UVjMWkrstNQp4oYPIxLnDKZQeeT5HWqMfwD6AwpuhZLDl04v n4zzccTJAVJJWJZi961Cw9/9Zb0bRw0= =MXJs -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmOMilAACgkQmmx57+YA GNlgnRAAptAAmfA2fxjAMM2hmgWfknj1/2JVtRdUzRUVvJbZ19y5rIOb0T06x3iH FktUge4oK0QLt9y4zzmS4dEg3zUEPFqHR4TEDfgZM78Q7lIUclM6ncuKuXeys2pS rj/8EwrXYyE4l9GrDEbv7dswxsR1CT+RPpbHUVIRhQy7eJenv/BV9din244VajE4 HpQt0wxp8op7NVPc4S+bbOsyY+0KH3LtSP8D+09Xjg6f3fGvBylzIqxKRJbmBgsJ MdjBZaWe6bxvhrAqojpuddtGhAy7atDb7VhGBjeIiPW1wnBAKmBGdHgYQvWOuxMG /4W6mwtjQf+JGG/y7D3QALKzlr4Ll75VUUF1ikBLv1od3XS6omQ6SsFNeYBvLG44 QyYkRgyVav6txfYgWZVQZwU8c9YGf/CIgf09NHoESNq/3fswBzbMogZ9gWnueDQ4 wwIh3gRHbjXYEwHF+k/U8KbEFvf73vK2VWITgse+fg7zIG5ir/zt/RAYjW8awAMM vEKHRaeBCgttYkiCc/ao4MmxEhVGZX9+SmPzYMjVLTndng2Hc7d9KOBBWil+S9DI pTqN39ZOjN5y6DTCQYYtoolq4CWOKmXZfnMKp41J641c5Yj7bfs597uuMVz/wkfG OZgfRSUQ9HHK4UpiDtj+fcA6EaXJYg34JbFa4wzywFrkm/tI/sQ= =L7ez -----END PGP SIGNATURE----- Merge tag 'asahi-soc-dt-6.2-v2' of https://github.com/AsahiLinux/linux into soc/dt Apple SoC DT updates for 6.2 (v2). This includes: * L1/L2 cache topology for t600x * CPUfreq nodes for t8103/t600x * DT binding for CPUfreq * Associated MAINTAINERS update The CPUfreq driver was already merged for 6.2 via its tree. * tag 'asahi-soc-dt-6.2-v2' of https://github.com/AsahiLinux/linux: arm64: dts: apple: Add CPU topology & cpufreq nodes for t600x arm64: dts: apple: Add CPU topology & cpufreq nodes for t8103 dt-bindings: cpufreq: apple,soc-cpufreq: Add binding for Apple SoC cpufreq MAINTAINERS: Add entries for Apple SoC cpufreq driver arm64: dts: apple: Add t600x L1/L2 cache properties and nodes Link: https://lore.kernel.org/r/a9353121-7fed-fde7-6f40-939a65bfeefb@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
8bc638ea67
|
|
@ -0,0 +1,117 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SoC cluster cpufreq device
|
||||
|
||||
maintainers:
|
||||
- Hector Martin <marcan@marcan.st>
|
||||
|
||||
description: |
|
||||
Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
|
||||
the cluster management register block. This binding uses the standard
|
||||
operating-points-v2 table to define the CPU performance states, with the
|
||||
opp-level property specifying the hardware p-state index for that level.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- apple,t8103-cluster-cpufreq
|
||||
- apple,t8112-cluster-cpufreq
|
||||
- const: apple,cluster-cpufreq
|
||||
- items:
|
||||
- const: apple,t6000-cluster-cpufreq
|
||||
- const: apple,t8103-cluster-cpufreq
|
||||
- const: apple,cluster-cpufreq
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#performance-domain-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#performance-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// This example shows a single CPU per domain and 2 domains,
|
||||
// with two p-states per domain.
|
||||
// Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
operating-points-v2 = <&ecluster_opp>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
compatible = "apple,firestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10100>;
|
||||
operating-points-v2 = <&pcluster_opp>;
|
||||
performance-domains = <&cpufreq_p>;
|
||||
};
|
||||
};
|
||||
|
||||
ecluster_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <7500>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <972000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <22000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcluster_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <8000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <828000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <19000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpufreq_e: performance-controller@210e20000 {
|
||||
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x10e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
cpufreq_p: performance-controller@211e20000 {
|
||||
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x11e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1897,6 +1897,7 @@ T: git https://github.com/AsahiLinux/linux.git
|
|||
F: Documentation/devicetree/bindings/arm/apple.yaml
|
||||
F: Documentation/devicetree/bindings/arm/apple/*
|
||||
F: Documentation/devicetree/bindings/clock/apple,nco.yaml
|
||||
F: Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
|
||||
F: Documentation/devicetree/bindings/dma/apple,admac.yaml
|
||||
F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/apple,*
|
||||
|
|
@ -1911,6 +1912,7 @@ F: Documentation/devicetree/bindings/power/apple*
|
|||
F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
|
||||
F: arch/arm64/boot/dts/apple/
|
||||
F: drivers/clk/clk-apple-nco.c
|
||||
F: drivers/cpufreq/apple-soc-cpufreq.c
|
||||
F: drivers/dma/apple-admac.c
|
||||
F: drivers/i2c/busses/i2c-pasemi-core.c
|
||||
F: drivers/i2c/busses/i2c-pasemi-platform.c
|
||||
|
|
|
|||
|
|
@ -23,12 +23,59 @@
|
|||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
cpu-map {
|
||||
cluster3 {
|
||||
core0 {
|
||||
cpu = <&cpu_e10>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_e11>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster4 {
|
||||
core0 {
|
||||
cpu = <&cpu_p20>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p21>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p22>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p23>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster5 {
|
||||
core0 {
|
||||
cpu = <&cpu_p30>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p31>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p32>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p33>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_e10: cpu@800 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x800>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_3>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&icestorm_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e_die1>;
|
||||
};
|
||||
|
||||
cpu_e11: cpu@801 {
|
||||
|
|
@ -37,6 +84,12 @@
|
|||
reg = <0x0 0x801>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_3>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&icestorm_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e_die1>;
|
||||
};
|
||||
|
||||
cpu_p20: cpu@10900 {
|
||||
|
|
@ -45,6 +98,12 @@
|
|||
reg = <0x0 0x10900>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_4>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0_die1>;
|
||||
};
|
||||
|
||||
cpu_p21: cpu@10901 {
|
||||
|
|
@ -53,6 +112,12 @@
|
|||
reg = <0x0 0x10901>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_4>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0_die1>;
|
||||
};
|
||||
|
||||
cpu_p22: cpu@10902 {
|
||||
|
|
@ -61,6 +126,12 @@
|
|||
reg = <0x0 0x10902>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_4>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0_die1>;
|
||||
};
|
||||
|
||||
cpu_p23: cpu@10903 {
|
||||
|
|
@ -69,6 +140,12 @@
|
|||
reg = <0x0 0x10903>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_4>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0_die1>;
|
||||
};
|
||||
|
||||
cpu_p30: cpu@10a00 {
|
||||
|
|
@ -77,6 +154,12 @@
|
|||
reg = <0x0 0x10a00>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_5>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1_die1>;
|
||||
};
|
||||
|
||||
cpu_p31: cpu@10a01 {
|
||||
|
|
@ -85,6 +168,12 @@
|
|||
reg = <0x0 0x10a01>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_5>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1_die1>;
|
||||
};
|
||||
|
||||
cpu_p32: cpu@10a02 {
|
||||
|
|
@ -93,6 +182,12 @@
|
|||
reg = <0x0 0x10a02>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_5>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1_die1>;
|
||||
};
|
||||
|
||||
cpu_p33: cpu@10a03 {
|
||||
|
|
@ -101,6 +196,33 @@
|
|||
reg = <0x0 0x10a03>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_5>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1_die1>;
|
||||
};
|
||||
|
||||
l2_cache_3: l2-cache-3 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x400000>;
|
||||
};
|
||||
|
||||
l2_cache_4: l2-cache-4 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0xc00000>;
|
||||
};
|
||||
|
||||
l2_cache_5: l2-cache-5 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0xc00000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -155,7 +277,6 @@
|
|||
#undef DIE
|
||||
#undef DIE_NO
|
||||
|
||||
|
||||
&aic {
|
||||
affinities {
|
||||
e-core-pmu-affinity {
|
||||
|
|
|
|||
|
|
@ -15,12 +15,59 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu_e00>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_e01>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu_p00>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p01>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p02>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p03>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&cpu_p10>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p11>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p12>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_e00: cpu@0 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_0>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&icestorm_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu_e01: cpu@1 {
|
||||
|
|
@ -29,6 +76,12 @@
|
|||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_0>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&icestorm_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu_p00: cpu@10100 {
|
||||
|
|
@ -37,6 +90,12 @@
|
|||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p01: cpu@10101 {
|
||||
|
|
@ -45,6 +104,12 @@
|
|||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p02: cpu@10102 {
|
||||
|
|
@ -53,6 +118,12 @@
|
|||
reg = <0x0 0x10102>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p03: cpu@10103 {
|
||||
|
|
@ -61,6 +132,12 @@
|
|||
reg = <0x0 0x10103>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p10: cpu@10200 {
|
||||
|
|
@ -69,6 +146,12 @@
|
|||
reg = <0x0 0x10200>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
cpu_p11: cpu@10201 {
|
||||
|
|
@ -77,6 +160,12 @@
|
|||
reg = <0x0 0x10201>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
cpu_p12: cpu@10202 {
|
||||
|
|
@ -85,6 +174,12 @@
|
|||
reg = <0x0 0x10202>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
cpu_p13: cpu@10203 {
|
||||
|
|
@ -93,7 +188,149 @@
|
|||
reg = <0x0 0x10203>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&firestorm_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
l2_cache_0: l2-cache-0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x400000>;
|
||||
};
|
||||
|
||||
l2_cache_1: l2-cache-1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0xc00000>;
|
||||
};
|
||||
|
||||
l2_cache_2: l2-cache-2 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0xc00000>;
|
||||
};
|
||||
};
|
||||
|
||||
icestorm_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <7500>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <972000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <23000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1332000000>;
|
||||
opp-level = <3>;
|
||||
clock-latency-ns = <29000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1704000000>;
|
||||
opp-level = <4>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <2064000000>;
|
||||
opp-level = <5>;
|
||||
clock-latency-ns = <50000>;
|
||||
};
|
||||
};
|
||||
|
||||
firestorm_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <8000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <828000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <18000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-level = <3>;
|
||||
clock-latency-ns = <19000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1296000000>;
|
||||
opp-level = <4>;
|
||||
clock-latency-ns = <23000>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <1524000000>;
|
||||
opp-level = <5>;
|
||||
clock-latency-ns = <24000>;
|
||||
};
|
||||
opp06 {
|
||||
opp-hz = /bits/ 64 <1752000000>;
|
||||
opp-level = <6>;
|
||||
clock-latency-ns = <28000>;
|
||||
};
|
||||
opp07 {
|
||||
opp-hz = /bits/ 64 <1980000000>;
|
||||
opp-level = <7>;
|
||||
clock-latency-ns = <31000>;
|
||||
};
|
||||
opp08 {
|
||||
opp-hz = /bits/ 64 <2208000000>;
|
||||
opp-level = <8>;
|
||||
clock-latency-ns = <45000>;
|
||||
};
|
||||
opp09 {
|
||||
opp-hz = /bits/ 64 <2448000000>;
|
||||
opp-level = <9>;
|
||||
clock-latency-ns = <49000>;
|
||||
};
|
||||
opp10 {
|
||||
opp-hz = /bits/ 64 <2676000000>;
|
||||
opp-level = <10>;
|
||||
clock-latency-ns = <53000>;
|
||||
};
|
||||
opp11 {
|
||||
opp-hz = /bits/ 64 <2904000000>;
|
||||
opp-level = <11>;
|
||||
clock-latency-ns = <56000>;
|
||||
};
|
||||
opp12 {
|
||||
opp-hz = /bits/ 64 <3036000000>;
|
||||
opp-level = <12>;
|
||||
clock-latency-ns = <56000>;
|
||||
};
|
||||
/* Not available until CPU deep sleep is implemented
|
||||
opp13 {
|
||||
opp-hz = /bits/ 64 <3132000000>;
|
||||
opp-level = <13>;
|
||||
clock-latency-ns = <56000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp14 {
|
||||
opp-hz = /bits/ 64 <3168000000>;
|
||||
opp-level = <14>;
|
||||
clock-latency-ns = <56000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp15 {
|
||||
opp-hz = /bits/ 64 <3228000000>;
|
||||
opp-level = <15>;
|
||||
clock-latency-ns = <56000>;
|
||||
turbo-mode;
|
||||
};
|
||||
*/
|
||||
};
|
||||
|
||||
pmu-e {
|
||||
|
|
|
|||
|
|
@ -6,6 +6,24 @@
|
|||
* Copyright The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
DIE_NODE(cpufreq_e): cpufreq@210e20000 {
|
||||
compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x10e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(cpufreq_p0): cpufreq@211e20000 {
|
||||
compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x11e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(cpufreq_p1): cpufreq@212e20000 {
|
||||
compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x12e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(pmgr): power-management@28e080000 {
|
||||
compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -22,71 +22,243 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu_e0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_e1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_e2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_e3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu_p0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_e0: cpu@0 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&ecluster_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
cpu_e1: cpu@1 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&ecluster_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
cpu_e2: cpu@2 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&ecluster_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
cpu_e3: cpu@3 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&ecluster_opp>;
|
||||
capacity-dmips-mhz = <714>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu4: cpu@10100 {
|
||||
cpu_p0: cpu@10100 {
|
||||
compatible = "apple,firestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&pcluster_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p>;
|
||||
};
|
||||
|
||||
cpu5: cpu@10101 {
|
||||
cpu_p1: cpu@10101 {
|
||||
compatible = "apple,firestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&pcluster_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p>;
|
||||
};
|
||||
|
||||
cpu6: cpu@10102 {
|
||||
cpu_p2: cpu@10102 {
|
||||
compatible = "apple,firestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10102>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&pcluster_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p>;
|
||||
};
|
||||
|
||||
cpu7: cpu@10103 {
|
||||
cpu_p3: cpu@10103 {
|
||||
compatible = "apple,firestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10103>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
operating-points-v2 = <&pcluster_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p>;
|
||||
};
|
||||
};
|
||||
|
||||
ecluster_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <7500>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <972000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <22000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1332000000>;
|
||||
opp-level = <3>;
|
||||
clock-latency-ns = <27000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1704000000>;
|
||||
opp-level = <4>;
|
||||
clock-latency-ns = <33000>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <2064000000>;
|
||||
opp-level = <5>;
|
||||
clock-latency-ns = <50000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcluster_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <8000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <828000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <19000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-level = <3>;
|
||||
clock-latency-ns = <21000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1284000000>;
|
||||
opp-level = <4>;
|
||||
clock-latency-ns = <23000>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-level = <5>;
|
||||
clock-latency-ns = <24000>;
|
||||
};
|
||||
opp06 {
|
||||
opp-hz = /bits/ 64 <1728000000>;
|
||||
opp-level = <6>;
|
||||
clock-latency-ns = <29000>;
|
||||
};
|
||||
opp07 {
|
||||
opp-hz = /bits/ 64 <1956000000>;
|
||||
opp-level = <7>;
|
||||
clock-latency-ns = <31000>;
|
||||
};
|
||||
opp08 {
|
||||
opp-hz = /bits/ 64 <2184000000>;
|
||||
opp-level = <8>;
|
||||
clock-latency-ns = <34000>;
|
||||
};
|
||||
opp09 {
|
||||
opp-hz = /bits/ 64 <2388000000>;
|
||||
opp-level = <9>;
|
||||
clock-latency-ns = <36000>;
|
||||
};
|
||||
opp10 {
|
||||
opp-hz = /bits/ 64 <2592000000>;
|
||||
opp-level = <10>;
|
||||
clock-latency-ns = <51000>;
|
||||
};
|
||||
opp11 {
|
||||
opp-hz = /bits/ 64 <2772000000>;
|
||||
opp-level = <11>;
|
||||
clock-latency-ns = <54000>;
|
||||
};
|
||||
opp12 {
|
||||
opp-hz = /bits/ 64 <2988000000>;
|
||||
opp-level = <12>;
|
||||
clock-latency-ns = <55000>;
|
||||
};
|
||||
#if 0
|
||||
/* Not available until CPU deep sleep is implemented */
|
||||
opp13 {
|
||||
opp-hz = /bits/ 64 <3096000000>;
|
||||
opp-level = <13>;
|
||||
clock-latency-ns = <55000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp14 {
|
||||
opp-hz = /bits/ 64 <3144000000>;
|
||||
opp-level = <14>;
|
||||
clock-latency-ns = <56000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp15 {
|
||||
opp-hz = /bits/ 64 <3204000000>;
|
||||
opp-level = <15>;
|
||||
clock-latency-ns = <56000>;
|
||||
turbo-mode;
|
||||
};
|
||||
#endif
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&aic>;
|
||||
|
|
@ -134,6 +306,18 @@
|
|||
ranges;
|
||||
nonposted-mmio;
|
||||
|
||||
cpufreq_e: performance-controller@210e20000 {
|
||||
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x10e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
cpufreq_p: performance-controller@211e20000 {
|
||||
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x11e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
dart_sio: iommu@235004000 {
|
||||
compatible = "apple,t8103-dart";
|
||||
reg = <0x2 0x35004000 0x0 0x4000>;
|
||||
|
|
@ -303,12 +487,12 @@
|
|||
affinities {
|
||||
e-core-pmu-affinity {
|
||||
apple,fiq-index = <AIC_CPU_PMU_E>;
|
||||
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
|
||||
cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
|
||||
};
|
||||
|
||||
p-core-pmu-affinity {
|
||||
apple,fiq-index = <AIC_CPU_PMU_P>;
|
||||
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
|
||||
cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче