nommu: Fix compressed/head.S to not perform MMU specific operations
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Родитель
0e0fe9219d
Коммит
8bdca0ac2b
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@ -438,6 +438,7 @@ ENDPROC(__setup_mmu)
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__armv4_mmu_cache_on:
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__armv4_mmu_cache_on:
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mov r12, lr
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mov r12, lr
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#ifdef CONFIG_MMU
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bl __setup_mmu
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bl __setup_mmu
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mov r0, #0
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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@ -451,10 +452,12 @@ __armv4_mmu_cache_on:
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bl __common_mmu_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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#endif
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mov pc, r12
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mov pc, r12
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__armv7_mmu_cache_on:
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__armv7_mmu_cache_on:
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mov r12, lr
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mov r12, lr
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#ifdef CONFIG_MMU
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mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
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mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
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tst r11, #0xf @ VMSA
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tst r11, #0xf @ VMSA
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blne __setup_mmu
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blne __setup_mmu
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@ -462,9 +465,11 @@ __armv7_mmu_cache_on:
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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tst r11, #0xf @ VMSA
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tst r11, #0xf @ VMSA
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mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x003c @ write buffer
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orr r0, r0, #0x003c @ write buffer
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#ifdef CONFIG_MMU
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#ifdef CONFIG_CPU_ENDIAN_BE8
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orr r0, r0, #1 << 25 @ big-endian page tables
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orr r0, r0, #1 << 25 @ big-endian page tables
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#endif
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#endif
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@ -472,6 +477,7 @@ __armv7_mmu_cache_on:
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movne r1, #-1
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movne r1, #-1
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mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
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mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
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mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
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mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ load control register
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mcr p15, 0, r0, c1, c0, 0 @ load control register
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mrc p15, 0, r0, c1, c0, 0 @ and read it back
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mrc p15, 0, r0, c1, c0, 0 @ and read it back
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mov r0, #0
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mov r0, #0
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@ -785,22 +791,30 @@ __armv3_mpu_cache_off:
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mov pc, lr
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mov pc, lr
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__armv4_mmu_cache_off:
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__armv4_mmu_cache_off:
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#ifdef CONFIG_MMU
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mrc p15, 0, r0, c1, c0
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mov r0, #0
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
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mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
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mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
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mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
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#endif
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mov pc, lr
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mov pc, lr
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__armv7_mmu_cache_off:
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__armv7_mmu_cache_off:
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mrc p15, 0, r0, c1, c0
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mrc p15, 0, r0, c1, c0
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#ifdef CONFIG_MMU
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bic r0, r0, #0x000d
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bic r0, r0, #0x000d
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#else
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bic r0, r0, #0x000c
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#endif
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mov r12, lr
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mov r12, lr
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bl __armv7_mmu_cache_flush
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bl __armv7_mmu_cache_flush
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mov r0, #0
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mov r0, #0
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
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mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
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#endif
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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