bcma: implement host code support for PCIe Gen 2 devices
This is stil incomplete, so we don't add PCI IDs of new devices yet. Purpose of this patch is to allow testing & adjusting rest of the code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -13,10 +13,12 @@
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static void bcma_host_pci_switch_core(struct bcma_device *core)
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{
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int win2 = core->bus->host_is_pcie2 ?
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BCMA_PCIE2_BAR0_WIN2 : BCMA_PCI_BAR0_WIN2;
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pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
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core->addr);
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pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
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core->wrap);
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pci_write_config_dword(core->bus->host_pci, win2, core->wrap);
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core->bus->mapped_core = core;
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bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
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}
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@ -318,6 +318,7 @@ struct bcma_bus {
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const struct bcma_host_ops *ops;
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enum bcma_hosttype hosttype;
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bool host_is_pcie2; /* Used for BCMA_HOSTTYPE_PCI only */
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union {
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/* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
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struct pci_dev *host_pci;
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@ -64,6 +64,8 @@
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#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
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#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
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#define BCMA_PCIE2_BAR0_WIN2 0x70
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/* SiliconBackplane Address Map.
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* All regions may not exist on all chips.
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*/
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