Revert "powerpc/powernv: Add support for the cxl kernel api on the real phb"
Remove abandonned capi support for the Mellanox CX4.
This reverts commit 4361b03430.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Alastair D'Silva
Michael Ellerman
Родитель
c8d43cf08a
Коммит
8bf6b91a51
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@ -50,13 +50,6 @@ int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev, int num);
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void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev);
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/* Support for the cxl kernel api on the real PHB (instead of vPHB) */
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int pnv_cxl_enable_phb_kernel_api(struct pci_controller *hose, bool enable);
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bool pnv_pci_on_cxl_phb(struct pci_dev *dev);
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struct cxl_afu *pnv_cxl_phb_to_afu(struct pci_controller *hose);
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void pnv_cxl_phb_set_peer_afu(struct pci_dev *dev, struct cxl_afu *afu);
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#endif
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struct pnv_php_slot {
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@ -8,10 +8,8 @@
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*/
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#include <linux/module.h>
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#include <asm/pci-bridge.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include <misc/cxl.h>
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#include "pci.h"
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@ -178,116 +176,3 @@ static inline int get_cxl_module(void)
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#else
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static inline int get_cxl_module(void) { return 0; }
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#endif
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/*
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* Sets flags and switches the controller ops to enable the cxl kernel api.
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* Originally the cxl kernel API operated on a virtual PHB, but certain cards
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* such as the Mellanox CX4 use a peer model instead and for these cards the
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* cxl kernel api will operate on the real PHB.
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*/
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int pnv_cxl_enable_phb_kernel_api(struct pci_controller *hose, bool enable)
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{
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struct pnv_phb *phb = hose->private_data;
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int rc;
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if (!enable) {
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/*
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* Once cxl mode is enabled on the PHB, there is currently no
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* known safe method to disable it again, and trying risks a
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* checkstop. If we can find a way to safely disable cxl mode
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* in the future we can revisit this, but for now the only sane
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* thing to do is to refuse to disable cxl mode:
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*/
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return -EPERM;
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}
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/*
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* Hold a reference to the cxl module since several PHB operations now
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* depend on it, and it would be insane to allow it to be removed so
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* long as we are in this mode (and since we can't safely disable this
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* mode once enabled...).
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*/
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rc = get_cxl_module();
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if (rc)
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return rc;
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phb->flags |= PNV_PHB_FLAG_CXL;
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hose->controller_ops = pnv_cxl_cx4_ioda_controller_ops;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_cxl_enable_phb_kernel_api);
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bool pnv_pci_on_cxl_phb(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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return !!(phb->flags & PNV_PHB_FLAG_CXL);
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}
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EXPORT_SYMBOL_GPL(pnv_pci_on_cxl_phb);
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struct cxl_afu *pnv_cxl_phb_to_afu(struct pci_controller *hose)
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{
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struct pnv_phb *phb = hose->private_data;
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return (struct cxl_afu *)phb->cxl_afu;
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}
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EXPORT_SYMBOL_GPL(pnv_cxl_phb_to_afu);
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void pnv_cxl_phb_set_peer_afu(struct pci_dev *dev, struct cxl_afu *afu)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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phb->cxl_afu = afu;
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}
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EXPORT_SYMBOL_GPL(pnv_cxl_phb_set_peer_afu);
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/*
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* In the peer cxl model, the XSL/PSL is physical function 0, and will be used
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* by other functions on the device for memory access and interrupts. When the
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* other functions are enabled we explicitly take a reference on the cxl
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* function since they will use it, and allocate a default context associated
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* with that function just like the vPHB model of the cxl kernel API.
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*/
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bool pnv_cxl_enable_device_hook(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct cxl_afu *afu = phb->cxl_afu;
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if (!pnv_pci_enable_device_hook(dev))
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return false;
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/* No special handling for the cxl function, which is always PF 0 */
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if (PCI_FUNC(dev->devfn) == 0)
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return true;
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if (!afu) {
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dev_WARN(&dev->dev, "Attempted to enable function > 0 on CXL PHB without a peer AFU\n");
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return false;
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}
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dev_info(&dev->dev, "Enabling function on CXL enabled PHB with peer AFU\n");
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/* Make sure the peer AFU can't go away while this device is active */
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cxl_afu_get(afu);
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return cxl_pci_associate_default_context(dev, afu);
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}
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void pnv_cxl_disable_device(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct cxl_afu *afu = phb->cxl_afu;
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/* No special handling for cxl function: */
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if (PCI_FUNC(dev->devfn) == 0)
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return;
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cxl_pci_disable_device(dev);
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cxl_afu_put(afu);
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}
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@ -3575,7 +3575,7 @@ static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
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/* Prevent enabling devices for which we couldn't properly
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* assign a PE
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*/
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bool pnv_pci_enable_device_hook(struct pci_dev *dev)
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static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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@ -3843,22 +3843,6 @@ static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
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.shutdown = pnv_pci_ioda_shutdown,
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};
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#ifdef CONFIG_CXL_BASE
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const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
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.dma_dev_setup = pnv_pci_dma_dev_setup,
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.dma_bus_setup = pnv_pci_dma_bus_setup,
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.enable_device_hook = pnv_cxl_enable_device_hook,
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.disable_device = pnv_cxl_disable_device,
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.release_device = pnv_pci_release_device,
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.window_alignment = pnv_pci_window_alignment,
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.setup_bridge = pnv_pci_setup_bridge,
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.reset_secondary_bus = pnv_pci_reset_secondary_bus,
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.dma_set_mask = pnv_pci_ioda_dma_set_mask,
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.dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
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.shutdown = pnv_pci_ioda_shutdown,
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};
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#endif
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static void __init pnv_pci_init_ioda_phb(struct device_node *np,
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u64 hub_id, int ioda_type)
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{
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@ -88,7 +88,6 @@ struct pnv_ioda_pe {
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};
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#define PNV_PHB_FLAG_EEH (1 << 0)
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#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
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struct pnv_phb {
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struct pci_controller *hose;
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@ -194,9 +193,6 @@ struct pnv_phb {
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bool nmmu_flush;
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} npu;
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#ifdef CONFIG_CXL_BASE
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struct cxl_afu *cxl_afu;
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#endif
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int p2p_target_count;
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};
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@ -238,7 +234,6 @@ extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
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extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
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extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
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extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
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extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
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extern int pnv_eeh_post_init(void);
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@ -262,12 +257,4 @@ extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
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extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
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extern int pnv_npu2_init(struct pnv_phb *phb);
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/* cxl functions */
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extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
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extern void pnv_cxl_disable_device(struct pci_dev *dev);
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/* phb ops (cxl switches these when enabling the kernel api on the phb) */
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extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
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#endif /* __POWERNV_PCI_H */
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