usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support to samsung-usbphy driver and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri <p.paneri@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Vivek Gautam
Felipe Balbi
Родитель
b506eebc50
Коммит
8c1b3e16e9
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@ -1,15 +1,23 @@
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* Samsung's usb phy transceiver
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The Samsung's phy transceiver is used for controlling usb otg phy for
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s3c-hsotg usb device controller.
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The Samsung's phy transceiver is used for controlling usb phy for
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s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
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across Samsung SOCs.
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TODO: Adding the PHY binding with controller(s) according to the under
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developement generic PHY driver.
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Required properties:
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Exynos4210:
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- compatible : should be "samsung,exynos4210-usbphy"
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- reg : base physical address of the phy registers and length of memory mapped
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region.
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Exynos5250:
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- compatible : should be "samsung,exynos5250-usbphy"
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- reg : base physical address of the phy registers and length of memory mapped
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region.
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Optional properties:
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- #address-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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@ -48,7 +48,7 @@ config USB_RCAR_PHY
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config SAMSUNG_USBPHY
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bool "Samsung USB PHY controller Driver"
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depends on USB_S3C_HSOTG
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depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
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select USB_OTG_UTILS
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help
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Enable this to support Samsung USB phy controller for samsung
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@ -5,7 +5,8 @@
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*
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* Author: Praveen Paneri <p.paneri@samsung.com>
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*
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* Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
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* Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
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* OHCI-EXYNOS controllers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -21,11 +22,13 @@
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/samsung_usb_phy.h>
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#include <linux/platform_data/samsung-usbphy.h>
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/* Register definitions */
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@ -57,24 +60,132 @@
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#define RSTCON_HLINK_SWRST (0x1 << 1)
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#define RSTCON_SWRST (0x1 << 0)
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/* EXYNOS5 */
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#define EXYNOS5_PHY_HOST_CTRL0 (0x00)
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#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
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#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
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#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
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#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
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#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
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#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
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#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
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#define FSEL_CLKSEL_50M (0x7)
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#define FSEL_CLKSEL_24M (0x5)
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#define FSEL_CLKSEL_20M (0x4)
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#define FSEL_CLKSEL_19200K (0x3)
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#define FSEL_CLKSEL_12M (0x2)
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#define FSEL_CLKSEL_10M (0x1)
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#define FSEL_CLKSEL_9600K (0x0)
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#define HOST_CTRL0_TESTBURNIN (0x1 << 11)
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#define HOST_CTRL0_RETENABLE (0x1 << 10)
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#define HOST_CTRL0_COMMONON_N (0x1 << 9)
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#define HOST_CTRL0_SIDDQ (0x1 << 6)
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#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
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#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
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#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
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#define HOST_CTRL0_UTMISWRST (0x1 << 2)
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#define HOST_CTRL0_LINKSWRST (0x1 << 1)
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#define HOST_CTRL0_PHYSWRST (0x1 << 0)
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#define EXYNOS5_PHY_HOST_TUNE0 (0x04)
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#define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
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#define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
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#define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
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#define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
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#define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
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#define HSIC_CTRL_REFCLKSEL (0x2 << 23)
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#define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
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#define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
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#define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
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#define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
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#define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
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#define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
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#define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
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#define HSIC_CTRL_SIDDQ (0x1 << 6)
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#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
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#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
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#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
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#define HSIC_CTRL_UTMISWRST (0x1 << 2)
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#define HSIC_CTRL_PHYSWRST (0x1 << 0)
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#define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
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#define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
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#define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
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#define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
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#define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
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#define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
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#define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
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#define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
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#define HOST_OHCICTRL_CNTSEL (0x1 << 1)
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#define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
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#define EXYNOS5_PHY_OTG_SYS (0x38)
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#define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
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#define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
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#define OTG_SYS_PHY0_SWRST (0x1 << 12)
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#define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
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#define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
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#define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
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#define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
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#define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
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#define OTG_SYS_COMMON_ON (0x1 << 7)
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#define OTG_SYS_FSEL_MASK (0x7 << 4)
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#define OTG_SYS_FSEL(_x) ((_x) << 4)
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#define OTG_SYS_FORCESLEEP (0x1 << 3)
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#define OTG_SYS_OTGDISABLE (0x1 << 2)
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#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
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#define OTG_SYS_FORCESUSPEND (0x1 << 0)
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#define EXYNOS5_PHY_OTG_TUNE (0x40)
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#ifndef MHZ
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#define MHZ (1000*1000)
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#endif
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#ifndef KHZ
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#define KHZ (1000)
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#endif
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#define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
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#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
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#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
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#define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
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enum samsung_cpu_type {
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TYPE_S3C64XX,
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TYPE_EXYNOS4210,
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TYPE_EXYNOS5250,
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};
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/*
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* struct samsung_usbphy_drvdata - driver data for various SoC variants
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* @cpu_type: machine identifier
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* @devphy_en_mask: device phy enable mask for PHY CONTROL register
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* @hostphy_en_mask: host phy enable mask for PHY CONTROL register
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* @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
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* mapped address of system controller.
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* @hostphy_reg_offset: offset to HOST PHY CONTROL register from
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* mapped address of system controller.
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*
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* Here we have a separate mask for device type phy.
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* Having different masks for host and device type phy helps
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@ -87,7 +198,9 @@ enum samsung_cpu_type {
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struct samsung_usbphy_drvdata {
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int cpu_type;
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int devphy_en_mask;
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int hostphy_en_mask;
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u32 devphy_reg_offset;
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u32 hostphy_reg_offset;
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};
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/*
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@ -98,8 +211,12 @@ struct samsung_usbphy_drvdata {
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* @clk: usb phy clock
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* @regs: usb phy controller registers memory base
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* @pmuregs: USB device PHY_CONTROL register memory base
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* @sysreg: USB2.0 PHY_CFG register memory base
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* @ref_clk_freq: reference clock frequency selection
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* @drv_data: driver data available for different SoCs
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* @phy_type: Samsung SoCs specific phy types: #HOST
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* #DEVICE
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* @phy_usage: usage count for phy
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* @lock: lock for phy operations
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*/
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struct samsung_usbphy {
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@ -109,13 +226,27 @@ struct samsung_usbphy {
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struct clk *clk;
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void __iomem *regs;
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void __iomem *pmuregs;
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void __iomem *sysreg;
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int ref_clk_freq;
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const struct samsung_usbphy_drvdata *drv_data;
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enum samsung_usb_phy_type phy_type;
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atomic_t phy_usage;
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spinlock_t lock;
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};
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#define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
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int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
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{
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if (!otg)
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return -ENODEV;
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if (!otg->host)
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otg->host = host;
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return 0;
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}
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static int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
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{
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struct device_node *usbphy_sys;
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@ -129,14 +260,27 @@ static int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
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sphy->pmuregs = of_iomap(usbphy_sys, 0);
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of_node_put(usbphy_sys);
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if (sphy->pmuregs == NULL) {
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dev_err(sphy->dev, "Can't get usb-phy pmu control register\n");
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return -ENODEV;
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goto err0;
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}
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sphy->sysreg = of_iomap(usbphy_sys, 1);
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/*
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* Not returning error code here, since this situation is not fatal.
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* Few SoCs may not have this switch available
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*/
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if (sphy->sysreg == NULL)
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dev_warn(sphy->dev, "Can't get usb-phy sysreg cfg register\n");
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of_node_put(usbphy_sys);
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return 0;
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err0:
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of_node_put(usbphy_sys);
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return -ENXIO;
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}
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/*
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@ -146,17 +290,42 @@ static int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
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*/
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static void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
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{
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void __iomem *reg;
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void __iomem *reg = NULL;
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u32 reg_val;
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u32 en_mask;
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u32 en_mask = 0;
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if (!sphy->pmuregs) {
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dev_warn(sphy->dev, "Can't set pmu isolation\n");
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return;
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}
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reg = sphy->pmuregs + sphy->drv_data->devphy_reg_offset;
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en_mask = sphy->drv_data->devphy_en_mask;
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switch (sphy->drv_data->cpu_type) {
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case TYPE_S3C64XX:
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/*
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* Do nothing: We will add here once S3C64xx goes for DT support
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*/
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break;
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case TYPE_EXYNOS4210:
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/*
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* Fall through since exynos4210 and exynos5250 have similar
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* register architecture: two separate registers for host and
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* device phy control with enable bit at position 0.
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*/
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case TYPE_EXYNOS5250:
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if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
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reg = sphy->pmuregs +
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sphy->drv_data->devphy_reg_offset;
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en_mask = sphy->drv_data->devphy_en_mask;
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} else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
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reg = sphy->pmuregs +
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sphy->drv_data->hostphy_reg_offset;
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en_mask = sphy->drv_data->hostphy_en_mask;
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}
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break;
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default:
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dev_err(sphy->dev, "Invalid SoC type\n");
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return;
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}
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reg_val = readl(reg);
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@ -168,6 +337,43 @@ static void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
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writel(reg_val, reg);
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}
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/*
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* Configure the mode of working of usb-phy here: HOST/DEVICE.
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*/
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static void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
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{
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u32 reg;
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if (!sphy->sysreg) {
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dev_warn(sphy->dev, "Can't configure specified phy mode\n");
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return;
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}
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reg = readl(sphy->sysreg);
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if (sphy->phy_type == USB_PHY_TYPE_DEVICE)
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reg &= ~EXYNOS_USB20PHY_CFG_HOST_LINK;
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else if (sphy->phy_type == USB_PHY_TYPE_HOST)
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reg |= EXYNOS_USB20PHY_CFG_HOST_LINK;
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writel(reg, sphy->sysreg);
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}
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/*
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* PHYs are different for USB Device and USB Host.
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* This make sure that correct PHY type is selected before
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* any operation on PHY.
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*/
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static int samsung_usbphy_set_type(struct usb_phy *phy,
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enum samsung_usb_phy_type phy_type)
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{
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struct samsung_usbphy *sphy = phy_to_sphy(phy);
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sphy->phy_type = phy_type;
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return 0;
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}
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/*
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* Returns reference clock frequency selection value
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*/
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@ -176,34 +382,185 @@ static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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struct clk *ref_clk;
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int refclk_freq = 0;
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ref_clk = clk_get(sphy->dev, "xusbxti");
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/*
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* In exynos5250 USB host and device PHY use
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* external crystal clock XXTI
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*/
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if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
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ref_clk = clk_get(sphy->dev, "ext_xtal");
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else
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ref_clk = clk_get(sphy->dev, "xusbxti");
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if (IS_ERR(ref_clk)) {
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dev_err(sphy->dev, "Failed to get reference clock\n");
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return PTR_ERR(ref_clk);
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}
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switch (clk_get_rate(ref_clk)) {
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case 12 * MHZ:
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refclk_freq = PHYCLK_CLKSEL_12M;
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break;
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case 24 * MHZ:
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refclk_freq = PHYCLK_CLKSEL_24M;
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break;
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case 48 * MHZ:
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refclk_freq = PHYCLK_CLKSEL_48M;
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break;
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default:
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if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
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refclk_freq = PHYCLK_CLKSEL_48M;
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else
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if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) {
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/* set clock frequency for PLL */
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switch (clk_get_rate(ref_clk)) {
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case 9600 * KHZ:
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refclk_freq = FSEL_CLKSEL_9600K;
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break;
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case 10 * MHZ:
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refclk_freq = FSEL_CLKSEL_10M;
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break;
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case 12 * MHZ:
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refclk_freq = FSEL_CLKSEL_12M;
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break;
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case 19200 * KHZ:
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refclk_freq = FSEL_CLKSEL_19200K;
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break;
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case 20 * MHZ:
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refclk_freq = FSEL_CLKSEL_20M;
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break;
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case 50 * MHZ:
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refclk_freq = FSEL_CLKSEL_50M;
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break;
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case 24 * MHZ:
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default:
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/* default reference clock */
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refclk_freq = FSEL_CLKSEL_24M;
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break;
|
||||
}
|
||||
} else {
|
||||
switch (clk_get_rate(ref_clk)) {
|
||||
case 12 * MHZ:
|
||||
refclk_freq = PHYCLK_CLKSEL_12M;
|
||||
break;
|
||||
case 24 * MHZ:
|
||||
refclk_freq = PHYCLK_CLKSEL_24M;
|
||||
break;
|
||||
break;
|
||||
case 48 * MHZ:
|
||||
refclk_freq = PHYCLK_CLKSEL_48M;
|
||||
break;
|
||||
default:
|
||||
if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
|
||||
refclk_freq = PHYCLK_CLKSEL_48M;
|
||||
else
|
||||
refclk_freq = PHYCLK_CLKSEL_24M;
|
||||
break;
|
||||
}
|
||||
}
|
||||
clk_put(ref_clk);
|
||||
|
||||
return refclk_freq;
|
||||
}
|
||||
|
||||
static bool exynos5_phyhost_is_on(void *regs)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
|
||||
|
||||
return !(reg & HOST_CTRL0_SIDDQ);
|
||||
}
|
||||
|
||||
static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
|
||||
{
|
||||
void __iomem *regs = sphy->regs;
|
||||
u32 phyclk = sphy->ref_clk_freq;
|
||||
u32 phyhost;
|
||||
u32 phyotg;
|
||||
u32 phyhsic;
|
||||
u32 ehcictrl;
|
||||
u32 ohcictrl;
|
||||
|
||||
/*
|
||||
* phy_usage helps in keeping usage count for phy
|
||||
* so that the first consumer enabling the phy is also
|
||||
* the last consumer to disable it.
|
||||
*/
|
||||
|
||||
atomic_inc(&sphy->phy_usage);
|
||||
|
||||
if (exynos5_phyhost_is_on(regs)) {
|
||||
dev_info(sphy->dev, "Already power on PHY\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Host configuration */
|
||||
phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
|
||||
|
||||
/* phy reference clock configuration */
|
||||
phyhost &= ~HOST_CTRL0_FSEL_MASK;
|
||||
phyhost |= HOST_CTRL0_FSEL(phyclk);
|
||||
|
||||
/* host phy reset */
|
||||
phyhost &= ~(HOST_CTRL0_PHYSWRST |
|
||||
HOST_CTRL0_PHYSWRSTALL |
|
||||
HOST_CTRL0_SIDDQ |
|
||||
/* Enable normal mode of operation */
|
||||
HOST_CTRL0_FORCESUSPEND |
|
||||
HOST_CTRL0_FORCESLEEP);
|
||||
|
||||
/* Link reset */
|
||||
phyhost |= (HOST_CTRL0_LINKSWRST |
|
||||
HOST_CTRL0_UTMISWRST |
|
||||
/* COMMON Block configuration during suspend */
|
||||
HOST_CTRL0_COMMONON_N);
|
||||
writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
|
||||
udelay(10);
|
||||
phyhost &= ~(HOST_CTRL0_LINKSWRST |
|
||||
HOST_CTRL0_UTMISWRST);
|
||||
writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
|
||||
|
||||
/* OTG configuration */
|
||||
phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
|
||||
|
||||
/* phy reference clock configuration */
|
||||
phyotg &= ~OTG_SYS_FSEL_MASK;
|
||||
phyotg |= OTG_SYS_FSEL(phyclk);
|
||||
|
||||
/* Enable normal mode of operation */
|
||||
phyotg &= ~(OTG_SYS_FORCESUSPEND |
|
||||
OTG_SYS_SIDDQ_UOTG |
|
||||
OTG_SYS_FORCESLEEP |
|
||||
OTG_SYS_REFCLKSEL_MASK |
|
||||
/* COMMON Block configuration during suspend */
|
||||
OTG_SYS_COMMON_ON);
|
||||
|
||||
/* OTG phy & link reset */
|
||||
phyotg |= (OTG_SYS_PHY0_SWRST |
|
||||
OTG_SYS_LINKSWRST_UOTG |
|
||||
OTG_SYS_PHYLINK_SWRESET |
|
||||
OTG_SYS_OTGDISABLE |
|
||||
/* Set phy refclk */
|
||||
OTG_SYS_REFCLKSEL_CLKCORE);
|
||||
|
||||
writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
|
||||
udelay(10);
|
||||
phyotg &= ~(OTG_SYS_PHY0_SWRST |
|
||||
OTG_SYS_LINKSWRST_UOTG |
|
||||
OTG_SYS_PHYLINK_SWRESET);
|
||||
writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
|
||||
|
||||
/* HSIC phy configuration */
|
||||
phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
|
||||
HSIC_CTRL_REFCLKSEL |
|
||||
HSIC_CTRL_PHYSWRST);
|
||||
writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
|
||||
writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
|
||||
udelay(10);
|
||||
phyhsic &= ~HSIC_CTRL_PHYSWRST;
|
||||
writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
|
||||
writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
|
||||
|
||||
udelay(80);
|
||||
|
||||
/* enable EHCI DMA burst */
|
||||
ehcictrl = readl(regs + EXYNOS5_PHY_HOST_EHCICTRL);
|
||||
ehcictrl |= (HOST_EHCICTRL_ENAINCRXALIGN |
|
||||
HOST_EHCICTRL_ENAINCR4 |
|
||||
HOST_EHCICTRL_ENAINCR8 |
|
||||
HOST_EHCICTRL_ENAINCR16);
|
||||
writel(ehcictrl, regs + EXYNOS5_PHY_HOST_EHCICTRL);
|
||||
|
||||
/* set ohci_suspend_on_n */
|
||||
ohcictrl = readl(regs + EXYNOS5_PHY_HOST_OHCICTRL);
|
||||
ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
|
||||
writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
|
||||
}
|
||||
|
||||
static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
|
||||
{
|
||||
void __iomem *regs = sphy->regs;
|
||||
|
|
@ -239,6 +596,41 @@ static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
|
|||
writel(rstcon, regs + SAMSUNG_RSTCON);
|
||||
}
|
||||
|
||||
static void samsung_exynos5_usbphy_disable(struct samsung_usbphy *sphy)
|
||||
{
|
||||
void __iomem *regs = sphy->regs;
|
||||
u32 phyhost;
|
||||
u32 phyotg;
|
||||
u32 phyhsic;
|
||||
|
||||
if (atomic_dec_return(&sphy->phy_usage) > 0) {
|
||||
dev_info(sphy->dev, "still being used\n");
|
||||
return;
|
||||
}
|
||||
|
||||
phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
|
||||
HSIC_CTRL_REFCLKSEL |
|
||||
HSIC_CTRL_SIDDQ |
|
||||
HSIC_CTRL_FORCESLEEP |
|
||||
HSIC_CTRL_FORCESUSPEND);
|
||||
writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
|
||||
writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
|
||||
|
||||
phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
|
||||
phyhost |= (HOST_CTRL0_SIDDQ |
|
||||
HOST_CTRL0_FORCESUSPEND |
|
||||
HOST_CTRL0_FORCESLEEP |
|
||||
HOST_CTRL0_PHYSWRST |
|
||||
HOST_CTRL0_PHYSWRSTALL);
|
||||
writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
|
||||
|
||||
phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
|
||||
phyotg |= (OTG_SYS_FORCESUSPEND |
|
||||
OTG_SYS_SIDDQ_UOTG |
|
||||
OTG_SYS_FORCESLEEP);
|
||||
writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
|
||||
}
|
||||
|
||||
static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
|
||||
{
|
||||
void __iomem *regs = sphy->regs;
|
||||
|
|
@ -266,11 +658,14 @@ static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
|
|||
static int samsung_usbphy_init(struct usb_phy *phy)
|
||||
{
|
||||
struct samsung_usbphy *sphy;
|
||||
struct usb_bus *host = NULL;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
|
||||
sphy = phy_to_sphy(phy);
|
||||
|
||||
host = phy->otg->host;
|
||||
|
||||
/* Enable the phy clock */
|
||||
ret = clk_prepare_enable(sphy->clk);
|
||||
if (ret) {
|
||||
|
|
@ -280,19 +675,35 @@ static int samsung_usbphy_init(struct usb_phy *phy)
|
|||
|
||||
spin_lock_irqsave(&sphy->lock, flags);
|
||||
|
||||
if (host) {
|
||||
/* setting default phy-type for USB 2.0 */
|
||||
if (!strstr(dev_name(host->controller), "ehci") ||
|
||||
!strstr(dev_name(host->controller), "ohci"))
|
||||
samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
|
||||
} else {
|
||||
samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
|
||||
}
|
||||
|
||||
/* Disable phy isolation */
|
||||
if (sphy->plat && sphy->plat->pmu_isolation)
|
||||
sphy->plat->pmu_isolation(false);
|
||||
else
|
||||
samsung_usbphy_set_isolation(sphy, false);
|
||||
|
||||
/* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
|
||||
samsung_usbphy_cfg_sel(sphy);
|
||||
|
||||
/* Initialize usb phy registers */
|
||||
samsung_usbphy_enable(sphy);
|
||||
if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
|
||||
samsung_exynos5_usbphy_enable(sphy);
|
||||
else
|
||||
samsung_usbphy_enable(sphy);
|
||||
|
||||
spin_unlock_irqrestore(&sphy->lock, flags);
|
||||
|
||||
/* Disable the phy clock */
|
||||
clk_disable_unprepare(sphy->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -302,10 +713,13 @@ static int samsung_usbphy_init(struct usb_phy *phy)
|
|||
static void samsung_usbphy_shutdown(struct usb_phy *phy)
|
||||
{
|
||||
struct samsung_usbphy *sphy;
|
||||
struct usb_bus *host = NULL;
|
||||
unsigned long flags;
|
||||
|
||||
sphy = phy_to_sphy(phy);
|
||||
|
||||
host = phy->otg->host;
|
||||
|
||||
if (clk_prepare_enable(sphy->clk)) {
|
||||
dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
|
||||
return;
|
||||
|
|
@ -313,8 +727,20 @@ static void samsung_usbphy_shutdown(struct usb_phy *phy)
|
|||
|
||||
spin_lock_irqsave(&sphy->lock, flags);
|
||||
|
||||
if (host) {
|
||||
/* setting default phy-type for USB 2.0 */
|
||||
if (!strstr(dev_name(host->controller), "ehci") ||
|
||||
!strstr(dev_name(host->controller), "ohci"))
|
||||
samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
|
||||
} else {
|
||||
samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
|
||||
}
|
||||
|
||||
/* De-initialize usb phy registers */
|
||||
samsung_usbphy_disable(sphy);
|
||||
if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
|
||||
samsung_exynos5_usbphy_disable(sphy);
|
||||
else
|
||||
samsung_usbphy_disable(sphy);
|
||||
|
||||
/* Enable phy isolation */
|
||||
if (sphy->plat && sphy->plat->pmu_isolation)
|
||||
|
|
@ -346,7 +772,9 @@ static inline const struct samsung_usbphy_drvdata
|
|||
static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct samsung_usbphy *sphy;
|
||||
struct usb_otg *otg;
|
||||
struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
|
||||
const struct samsung_usbphy_drvdata *drv_data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *phy_mem;
|
||||
void __iomem *phy_base;
|
||||
|
|
@ -369,7 +797,17 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
|
|||
if (!sphy)
|
||||
return -ENOMEM;
|
||||
|
||||
clk = devm_clk_get(dev, "otg");
|
||||
otg = devm_kzalloc(dev, sizeof(*otg), GFP_KERNEL);
|
||||
if (!otg)
|
||||
return -ENOMEM;
|
||||
|
||||
drv_data = samsung_usbphy_get_driver_data(pdev);
|
||||
|
||||
if (drv_data->cpu_type == TYPE_EXYNOS5250)
|
||||
clk = devm_clk_get(dev, "usbhost");
|
||||
else
|
||||
clk = devm_clk_get(dev, "otg");
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "Failed to get otg clock\n");
|
||||
return PTR_ERR(clk);
|
||||
|
|
@ -391,13 +829,17 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
|
|||
sphy->plat = pdata;
|
||||
sphy->regs = phy_base;
|
||||
sphy->clk = clk;
|
||||
sphy->drv_data = drv_data;
|
||||
sphy->phy.dev = sphy->dev;
|
||||
sphy->phy.label = "samsung-usbphy";
|
||||
sphy->phy.init = samsung_usbphy_init;
|
||||
sphy->phy.shutdown = samsung_usbphy_shutdown;
|
||||
sphy->drv_data = samsung_usbphy_get_driver_data(pdev);
|
||||
sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
|
||||
|
||||
sphy->phy.otg = otg;
|
||||
sphy->phy.otg->phy = &sphy->phy;
|
||||
sphy->phy.otg->set_host = samsung_usbphy_set_host;
|
||||
|
||||
spin_lock_init(&sphy->lock);
|
||||
|
||||
platform_set_drvdata(pdev, sphy);
|
||||
|
|
@ -413,6 +855,8 @@ static int __exit samsung_usbphy_remove(struct platform_device *pdev)
|
|||
|
||||
if (sphy->pmuregs)
|
||||
iounmap(sphy->pmuregs);
|
||||
if (sphy->sysreg)
|
||||
iounmap(sphy->sysreg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -425,6 +869,13 @@ static const struct samsung_usbphy_drvdata usbphy_s3c64xx = {
|
|||
static const struct samsung_usbphy_drvdata usbphy_exynos4 = {
|
||||
.cpu_type = TYPE_EXYNOS4210,
|
||||
.devphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
||||
.hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
||||
};
|
||||
|
||||
static struct samsung_usbphy_drvdata usbphy_exynos5 = {
|
||||
.cpu_type = TYPE_EXYNOS5250,
|
||||
.hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
||||
.hostphy_reg_offset = EXYNOS_USBHOST_PHY_CTRL_OFFSET,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
|
@ -435,6 +886,9 @@ static const struct of_device_id samsung_usbphy_dt_match[] = {
|
|||
}, {
|
||||
.compatible = "samsung,exynos4210-usbphy",
|
||||
.data = &usbphy_exynos4,
|
||||
}, {
|
||||
.compatible = "samsung,exynos5250-usbphy",
|
||||
.data = &usbphy_exynos5
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
|
@ -448,6 +902,9 @@ static struct platform_device_id samsung_usbphy_driver_ids[] = {
|
|||
}, {
|
||||
.name = "exynos4210-usbphy",
|
||||
.driver_data = (unsigned long)&usbphy_exynos4,
|
||||
}, {
|
||||
.name = "exynos5250-usbphy",
|
||||
.driver_data = (unsigned long)&usbphy_exynos5,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
|
|
|||
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