Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull clocksource updates from Ingo Molnar: "The main change in this tree is the addition of various new SoC clocksource/clockevents drivers: Conexant Digicolor SoCs, rockchip rk3288 board, asm9260 for MIPS and versatile AB/PB boards" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dts: versatile: Add sysregs node clocksource: versatile: Adapt for Versatile AB and PB boards dt/bindings: Add binding for Versatile system registers clocksource: Driver for Conexant Digicolor SoC timer clocksource: devicetree: Document Conexant Digicolor timer binding clockevents: rockchip: Add rockchip timer for rk3288 ARM: clocksource: Add asm9260_timer driver clocksource: marco: Rename marco to atlas7 clocksource: sirf: Remove unused variable
This commit is contained in:
Linus Torvalds
Коммит
8c334ce8f0
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@ -0,0 +1,10 @@
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ARM Versatile system registers
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--------------------------------------
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This is a system control registers block, providing multiple low level
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platform functions like board detection and identification, software
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interrupt generation, MMC and NOR Flash control etc.
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Required node properties:
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- compatible value : = "arm,versatile-sysreg", "syscon"
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- reg : physical base address and the size of the registers window
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@ -0,0 +1,18 @@
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Conexant Digicolor SoCs Timer Controller
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Required properties:
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- compatible : should be "cnxt,cx92755-timer"
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- reg : Specifies base physical address and size of the "Agent Communication"
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timer registers
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- interrupts : Contains 8 interrupts, one for each timer
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- clocks: phandle to the main clock
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Example:
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timer@f0000fc0 {
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compatible = "cnxt,cx92755-timer";
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reg = <0xf0000fc0 0x40>;
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interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>;
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clocks = <&main_clk>;
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};
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@ -0,0 +1,18 @@
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Rockchip rk3288 timer
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Required properties:
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- compatible: shall be "rockchip,rk3288-timer"
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- reg: base address of the timer register starting with TIMERS CONTROL register
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- interrupts: should contain the interrupts for Timer0
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- clocks : must contain an entry for each entry in clock-names
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- clock-names : must include the following entries:
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"timer", "pclk"
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Example:
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timer: timer@ff810000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0xff810000 0x20>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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@ -974,7 +974,7 @@ S: Maintained
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F: arch/arm/mach-prima2/
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F: drivers/clk/sirf/
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F: drivers/clocksource/timer-prima2.c
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F: drivers/clocksource/timer-marco.c
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F: drivers/clocksource/timer-atlas7.c
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N: [^a-z]sirf
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ARM/EBSA110 MACHINE SUPPORT
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@ -252,6 +252,11 @@
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#size-cells = <1>;
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ranges = <0 0x10000000 0x10000>;
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sysreg@0 {
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compatible = "arm,versatile-sysreg", "syscon";
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reg = <0x00000 0x1000>;
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};
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aaci@4000 {
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compatible = "arm,primecell";
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reg = <0x4000 0x1000>;
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@ -11,6 +11,7 @@ config ARCH_ROCKCHIP
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select DW_APB_TIMER_OF
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select ROCKCHIP_TIMER
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select ARM_GLOBAL_TIMER
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select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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help
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@ -18,6 +18,9 @@ config CLKBLD_I8253
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config CLKSRC_MMIO
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bool
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config DIGICOLOR_TIMER
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bool
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config DW_APB_TIMER
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bool
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@ -26,6 +29,10 @@ config DW_APB_TIMER_OF
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select DW_APB_TIMER
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select CLKSRC_OF
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config ROCKCHIP_TIMER
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bool
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select CLKSRC_OF
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config ARMADA_370_XP_TIMER
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bool
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select CLKSRC_OF
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@ -236,4 +243,14 @@ config CLKSRC_PXA
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This enables OST0 support available on PXA and SA-11x0
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platforms.
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config ASM9260_TIMER
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bool "Alphascale ASM9260 timer driver"
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depends on GENERIC_CLOCKEVENTS
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select CLKSRC_MMIO
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select CLKSRC_OF
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default y if MACH_ASM9260
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help
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This enables build of a clocksource and clockevent driver for
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the 32-bit System Timer hardware available on a Alphascale ASM9260.
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endmenu
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@ -10,15 +10,17 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
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obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
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obj-$(CONFIG_CLKBLD_I8253) += i8253.o
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obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
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obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
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obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
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obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
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obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
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obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
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obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
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obj-$(CONFIG_ORION_TIMER) += time-orion.o
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obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
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obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o
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obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
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obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o
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obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
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obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
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obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o
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@ -48,3 +50,4 @@ obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
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obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o
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obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
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obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
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obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
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@ -0,0 +1,220 @@
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/*
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/bitops.h>
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#define DRIVER_NAME "asm9260-timer"
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/*
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* this device provide 4 offsets for each register:
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* 0x0 - plain read write mode
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* 0x4 - set mode, OR logic.
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* 0x8 - clr mode, XOR logic.
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* 0xc - togle mode.
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*/
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#define SET_REG 4
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#define CLR_REG 8
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#define HW_IR 0x0000 /* RW. Interrupt */
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#define BM_IR_CR0 BIT(4)
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#define BM_IR_MR3 BIT(3)
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#define BM_IR_MR2 BIT(2)
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#define BM_IR_MR1 BIT(1)
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#define BM_IR_MR0 BIT(0)
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#define HW_TCR 0x0010 /* RW. Timer controller */
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/* BM_C*_RST
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* Timer Counter and the Prescale Counter are synchronously reset on the
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* next positive edge of PCLK. The counters remain reset until TCR[1] is
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* returned to zero. */
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#define BM_C3_RST BIT(7)
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#define BM_C2_RST BIT(6)
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#define BM_C1_RST BIT(5)
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#define BM_C0_RST BIT(4)
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/* BM_C*_EN
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* 1 - Timer Counter and Prescale Counter are enabled for counting
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* 0 - counters are disabled */
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#define BM_C3_EN BIT(3)
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#define BM_C2_EN BIT(2)
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#define BM_C1_EN BIT(1)
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#define BM_C0_EN BIT(0)
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#define HW_DIR 0x0020 /* RW. Direction? */
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/* 00 - count up
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* 01 - count down
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* 10 - ?? 2^n/2 */
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#define BM_DIR_COUNT_UP 0
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#define BM_DIR_COUNT_DOWN 1
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#define BM_DIR0_SHIFT 0
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#define BM_DIR1_SHIFT 4
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#define BM_DIR2_SHIFT 8
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#define BM_DIR3_SHIFT 12
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#define BM_DIR_DEFAULT (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \
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BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \
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BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \
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BM_DIR_COUNT_UP << BM_DIR3_SHIFT)
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#define HW_TC0 0x0030 /* RO. Timer counter 0 */
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/* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
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* interrupt. This registers can be used to detect overflow */
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#define HW_TC1 0x0040
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#define HW_TC2 0x0050
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#define HW_TC3 0x0060
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#define HW_PR 0x0070 /* RW. prescaler */
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#define BM_PR_DISABLE 0
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#define HW_PC 0x0080 /* RO. Prescaler counter */
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#define HW_MCR 0x0090 /* RW. Match control */
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/* enable interrupt on match */
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#define BM_MCR_INT_EN(n) (1 << (n * 3 + 0))
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/* enable TC reset on match */
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#define BM_MCR_RES_EN(n) (1 << (n * 3 + 1))
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/* enable stop TC on match */
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#define BM_MCR_STOP_EN(n) (1 << (n * 3 + 2))
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#define HW_MR0 0x00a0 /* RW. Match reg */
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#define HW_MR1 0x00b0
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#define HW_MR2 0x00C0
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#define HW_MR3 0x00D0
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#define HW_CTCR 0x0180 /* Counter control */
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#define BM_CTCR0_SHIFT 0
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#define BM_CTCR1_SHIFT 2
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#define BM_CTCR2_SHIFT 4
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#define BM_CTCR3_SHIFT 6
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#define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
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#define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \
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BM_CTCR_TM << BM_CTCR1_SHIFT | \
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BM_CTCR_TM << BM_CTCR2_SHIFT | \
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BM_CTCR_TM << BM_CTCR3_SHIFT)
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static struct asm9260_timer_priv {
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void __iomem *base;
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unsigned long ticks_per_jiffy;
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} priv;
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static int asm9260_timer_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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/* configure match count for TC0 */
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writel_relaxed(delta, priv.base + HW_MR0);
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/* enable TC0 */
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
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return 0;
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}
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static void asm9260_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* stop timer0 */
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* disable reset and stop on match */
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writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
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priv.base + HW_MCR + CLR_REG);
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/* configure match count for TC0 */
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writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
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/* enable TC0 */
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* enable reset and stop on match */
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writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
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priv.base + HW_MCR + SET_REG);
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break;
|
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default:
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break;
|
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}
|
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}
|
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|
||||
static struct clock_event_device event_dev = {
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.name = DRIVER_NAME,
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.rating = 200,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = asm9260_timer_set_next_event,
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.set_mode = asm9260_timer_set_mode,
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};
|
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|
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static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id)
|
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{
|
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struct clock_event_device *evt = dev_id;
|
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|
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evt->event_handler(evt);
|
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|
||||
writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
|
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|
||||
return IRQ_HANDLED;
|
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}
|
||||
|
||||
/*
|
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* ---------------------------------------------------------------------------
|
||||
* Timer initialization
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
static void __init asm9260_timer_init(struct device_node *np)
|
||||
{
|
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int irq;
|
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struct clk *clk;
|
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int ret;
|
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unsigned long rate;
|
||||
|
||||
priv.base = of_io_request_and_map(np, 0, np->name);
|
||||
if (!priv.base)
|
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panic("%s: unable to map resource", np->name);
|
||||
|
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clk = of_clk_get(np, 0);
|
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|
||||
ret = clk_prepare_enable(clk);
|
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if (ret)
|
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panic("Failed to enable clk!\n");
|
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|
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irq = irq_of_parse_and_map(np, 0);
|
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ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER,
|
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DRIVER_NAME, &event_dev);
|
||||
if (ret)
|
||||
panic("Failed to setup irq!\n");
|
||||
|
||||
/* set all timers for count-up */
|
||||
writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
|
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/* disable divider */
|
||||
writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
|
||||
/* make sure all timers use every rising PCLK edge. */
|
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writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
|
||||
/* enable interrupt for TC0 and clean setting for all other lines */
|
||||
writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
|
||||
200, 32, clocksource_mmio_readl_up);
|
||||
|
||||
/* Seems like we can't use counter without match register even if
|
||||
* actions for MR are disabled. So, set MR to max value. */
|
||||
writel_relaxed(0xffffffff, priv.base + HW_MR1);
|
||||
/* enable TC1 */
|
||||
writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
|
||||
|
||||
priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
|
||||
event_dev.cpumask = cpumask_of(0);
|
||||
clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
|
||||
asm9260_timer_init);
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Rockchip timer support
|
||||
*
|
||||
* Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#define TIMER_NAME "rk_timer"
|
||||
|
||||
#define TIMER_LOAD_COUNT0 0x00
|
||||
#define TIMER_LOAD_COUNT1 0x04
|
||||
#define TIMER_CONTROL_REG 0x10
|
||||
#define TIMER_INT_STATUS 0x18
|
||||
|
||||
#define TIMER_DISABLE 0x0
|
||||
#define TIMER_ENABLE 0x1
|
||||
#define TIMER_MODE_FREE_RUNNING (0 << 1)
|
||||
#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
|
||||
#define TIMER_INT_UNMASK (1 << 2)
|
||||
|
||||
struct bc_timer {
|
||||
struct clock_event_device ce;
|
||||
void __iomem *base;
|
||||
u32 freq;
|
||||
};
|
||||
|
||||
static struct bc_timer bc_timer;
|
||||
|
||||
static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
|
||||
{
|
||||
return container_of(ce, struct bc_timer, ce);
|
||||
}
|
||||
|
||||
static inline void __iomem *rk_base(struct clock_event_device *ce)
|
||||
{
|
||||
return rk_timer(ce)->base;
|
||||
}
|
||||
|
||||
static inline void rk_timer_disable(struct clock_event_device *ce)
|
||||
{
|
||||
writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
|
||||
dsb();
|
||||
}
|
||||
|
||||
static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
|
||||
{
|
||||
writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
|
||||
rk_base(ce) + TIMER_CONTROL_REG);
|
||||
dsb();
|
||||
}
|
||||
|
||||
static void rk_timer_update_counter(unsigned long cycles,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
|
||||
writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
|
||||
dsb();
|
||||
}
|
||||
|
||||
static void rk_timer_interrupt_clear(struct clock_event_device *ce)
|
||||
{
|
||||
writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
|
||||
dsb();
|
||||
}
|
||||
|
||||
static inline int rk_timer_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
rk_timer_disable(ce);
|
||||
rk_timer_update_counter(cycles, ce);
|
||||
rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void rk_timer_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
rk_timer_disable(ce);
|
||||
rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
|
||||
rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
rk_timer_disable(ce);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *ce = dev_id;
|
||||
|
||||
rk_timer_interrupt_clear(ce);
|
||||
|
||||
if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
|
||||
rk_timer_disable(ce);
|
||||
|
||||
ce->event_handler(ce);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void __init rk_timer_init(struct device_node *np)
|
||||
{
|
||||
struct clock_event_device *ce = &bc_timer.ce;
|
||||
struct clk *timer_clk;
|
||||
struct clk *pclk;
|
||||
int ret, irq;
|
||||
|
||||
bc_timer.base = of_iomap(np, 0);
|
||||
if (!bc_timer.base) {
|
||||
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
|
||||
return;
|
||||
}
|
||||
|
||||
pclk = of_clk_get_by_name(np, "pclk");
|
||||
if (IS_ERR(pclk)) {
|
||||
pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
|
||||
return;
|
||||
}
|
||||
|
||||
if (clk_prepare_enable(pclk)) {
|
||||
pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
|
||||
return;
|
||||
}
|
||||
|
||||
timer_clk = of_clk_get_by_name(np, "timer");
|
||||
if (IS_ERR(timer_clk)) {
|
||||
pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
|
||||
return;
|
||||
}
|
||||
|
||||
if (clk_prepare_enable(timer_clk)) {
|
||||
pr_err("Failed to enable timer clock\n");
|
||||
return;
|
||||
}
|
||||
|
||||
bc_timer.freq = clk_get_rate(timer_clk);
|
||||
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
if (irq == NO_IRQ) {
|
||||
pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
|
||||
return;
|
||||
}
|
||||
|
||||
ce->name = TIMER_NAME;
|
||||
ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
|
||||
ce->set_next_event = rk_timer_set_next_event;
|
||||
ce->set_mode = rk_timer_set_mode;
|
||||
ce->irq = irq;
|
||||
ce->cpumask = cpumask_of(0);
|
||||
ce->rating = 250;
|
||||
|
||||
rk_timer_interrupt_clear(ce);
|
||||
rk_timer_disable(ce);
|
||||
|
||||
ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
|
||||
if (ret) {
|
||||
pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
|
||||
return;
|
||||
}
|
||||
|
||||
clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
#define SIRFSOC_TIMER_REG_CNT 6
|
||||
|
||||
static unsigned long marco_timer_rate;
|
||||
static unsigned long atlas7_timer_rate;
|
||||
|
||||
static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
|
||||
SIRFSOC_TIMER_WATCHDOG_EN,
|
||||
|
|
@ -195,7 +195,7 @@ static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
|
|||
ce->rating = 200;
|
||||
ce->set_mode = sirfsoc_timer_set_mode;
|
||||
ce->set_next_event = sirfsoc_timer_set_next_event;
|
||||
clockevents_calc_mult_shift(ce, marco_timer_rate, 60);
|
||||
clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
|
||||
ce->max_delta_ns = clockevent_delta2ns(-2, ce);
|
||||
ce->min_delta_ns = clockevent_delta2ns(2, ce);
|
||||
ce->cpumask = cpumask_of(cpu);
|
||||
|
|
@ -255,9 +255,8 @@ static void __init sirfsoc_clockevent_init(void)
|
|||
}
|
||||
|
||||
/* initialize the kernel jiffy timer source */
|
||||
static void __init sirfsoc_marco_timer_init(struct device_node *np)
|
||||
static void __init sirfsoc_atlas7_timer_init(struct device_node *np)
|
||||
{
|
||||
u32 timer_div;
|
||||
struct clk *clk;
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
|
|
@ -265,7 +264,7 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)
|
|||
|
||||
BUG_ON(clk_prepare_enable(clk));
|
||||
|
||||
marco_timer_rate = clk_get_rate(clk);
|
||||
atlas7_timer_rate = clk_get_rate(clk);
|
||||
|
||||
/* timer dividers: 0, not divided */
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
|
|
@ -283,7 +282,7 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)
|
|||
/* Clear all interrupts */
|
||||
writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
|
||||
|
||||
BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, marco_timer_rate));
|
||||
BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));
|
||||
|
||||
sirfsoc_clockevent_init();
|
||||
}
|
||||
|
|
@ -302,6 +301,6 @@ static void __init sirfsoc_of_timer_init(struct device_node *np)
|
|||
if (!sirfsoc_timer1_irq.irq)
|
||||
panic("No irq passed for timer1 via DT\n");
|
||||
|
||||
sirfsoc_marco_timer_init(np);
|
||||
sirfsoc_atlas7_timer_init(np);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );
|
||||
CLOCKSOURCE_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* Conexant Digicolor timer driver
|
||||
*
|
||||
* Author: Baruch Siach <baruch@tkos.co.il>
|
||||
*
|
||||
* Copyright (C) 2014 Paradox Innovation Ltd.
|
||||
*
|
||||
* Based on:
|
||||
* Allwinner SoCs hstimer driver
|
||||
*
|
||||
* Copyright (C) 2013 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Conexant Digicolor SoCs have 8 configurable timers, named from "Timer A" to
|
||||
* "Timer H". Timer A is the only one with watchdog support, so it is dedicated
|
||||
* to the watchdog driver. This driver uses Timer B for sched_clock(), and
|
||||
* Timer C for clockevents.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/sched_clock.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
enum {
|
||||
TIMER_A,
|
||||
TIMER_B,
|
||||
TIMER_C,
|
||||
TIMER_D,
|
||||
TIMER_E,
|
||||
TIMER_F,
|
||||
TIMER_G,
|
||||
TIMER_H,
|
||||
};
|
||||
|
||||
#define CONTROL(t) ((t)*8)
|
||||
#define COUNT(t) ((t)*8 + 4)
|
||||
|
||||
#define CONTROL_DISABLE 0
|
||||
#define CONTROL_ENABLE BIT(0)
|
||||
#define CONTROL_MODE(m) ((m) << 4)
|
||||
#define CONTROL_MODE_ONESHOT CONTROL_MODE(1)
|
||||
#define CONTROL_MODE_PERIODIC CONTROL_MODE(2)
|
||||
|
||||
struct digicolor_timer {
|
||||
struct clock_event_device ce;
|
||||
void __iomem *base;
|
||||
u32 ticks_per_jiffy;
|
||||
int timer_id; /* one of TIMER_* */
|
||||
};
|
||||
|
||||
struct digicolor_timer *dc_timer(struct clock_event_device *ce)
|
||||
{
|
||||
return container_of(ce, struct digicolor_timer, ce);
|
||||
}
|
||||
|
||||
static inline void dc_timer_disable(struct clock_event_device *ce)
|
||||
{
|
||||
struct digicolor_timer *dt = dc_timer(ce);
|
||||
writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id));
|
||||
}
|
||||
|
||||
static inline void dc_timer_enable(struct clock_event_device *ce, u32 mode)
|
||||
{
|
||||
struct digicolor_timer *dt = dc_timer(ce);
|
||||
writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id));
|
||||
}
|
||||
|
||||
static inline void dc_timer_set_count(struct clock_event_device *ce,
|
||||
unsigned long count)
|
||||
{
|
||||
struct digicolor_timer *dt = dc_timer(ce);
|
||||
writel(count, dt->base + COUNT(dt->timer_id));
|
||||
}
|
||||
|
||||
static void digicolor_clkevt_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
struct digicolor_timer *dt = dc_timer(ce);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
dc_timer_disable(ce);
|
||||
dc_timer_set_count(ce, dt->ticks_per_jiffy);
|
||||
dc_timer_enable(ce, CONTROL_MODE_PERIODIC);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
dc_timer_disable(ce);
|
||||
dc_timer_enable(ce, CONTROL_MODE_ONESHOT);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
default:
|
||||
dc_timer_disable(ce);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int digicolor_clkevt_next_event(unsigned long evt,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
dc_timer_disable(ce);
|
||||
dc_timer_set_count(ce, evt);
|
||||
dc_timer_enable(ce, CONTROL_MODE_ONESHOT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct digicolor_timer dc_timer_dev = {
|
||||
.ce = {
|
||||
.name = "digicolor_tick",
|
||||
.rating = 340,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = digicolor_clkevt_mode,
|
||||
.set_next_event = digicolor_clkevt_next_event,
|
||||
},
|
||||
.timer_id = TIMER_C,
|
||||
};
|
||||
|
||||
static irqreturn_t digicolor_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = dev_id;
|
||||
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static u64 digicolor_timer_sched_read(void)
|
||||
{
|
||||
return ~readl(dc_timer_dev.base + COUNT(TIMER_B));
|
||||
}
|
||||
|
||||
static void __init digicolor_timer_init(struct device_node *node)
|
||||
{
|
||||
unsigned long rate;
|
||||
struct clk *clk;
|
||||
int ret, irq;
|
||||
|
||||
/*
|
||||
* timer registers are shared with the watchdog timer;
|
||||
* don't map exclusively
|
||||
*/
|
||||
dc_timer_dev.base = of_iomap(node, 0);
|
||||
if (!dc_timer_dev.base) {
|
||||
pr_err("Can't map registers");
|
||||
return;
|
||||
}
|
||||
|
||||
irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id);
|
||||
if (irq <= 0) {
|
||||
pr_err("Can't parse IRQ");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Can't get timer clock");
|
||||
return;
|
||||
}
|
||||
clk_prepare_enable(clk);
|
||||
rate = clk_get_rate(clk);
|
||||
dc_timer_dev.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
|
||||
|
||||
writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B));
|
||||
writel(UINT_MAX, dc_timer_dev.base + COUNT(TIMER_B));
|
||||
writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B));
|
||||
|
||||
sched_clock_register(digicolor_timer_sched_read, 32, rate);
|
||||
clocksource_mmio_init(dc_timer_dev.base + COUNT(TIMER_B), node->name,
|
||||
rate, 340, 32, clocksource_mmio_readl_down);
|
||||
|
||||
ret = request_irq(irq, digicolor_timer_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL, "digicolor_timerC",
|
||||
&dc_timer_dev.ce);
|
||||
if (ret)
|
||||
pr_warn("request of timer irq %d failed (%d)\n", irq, ret);
|
||||
|
||||
dc_timer_dev.ce.cpumask = cpu_possible_mask;
|
||||
dc_timer_dev.ce.irq = irq;
|
||||
|
||||
clockevents_config_and_register(&dc_timer_dev.ce, rate, 0, 0xffffffff);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer",
|
||||
digicolor_timer_init);
|
||||
|
|
@ -36,5 +36,7 @@ static void __init versatile_sched_clock_init(struct device_node *node)
|
|||
|
||||
sched_clock_register(versatile_sys_24mhz_read, 32, 24000000);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(versatile, "arm,vexpress-sysreg",
|
||||
CLOCKSOURCE_OF_DECLARE(vexpress, "arm,vexpress-sysreg",
|
||||
versatile_sched_clock_init);
|
||||
CLOCKSOURCE_OF_DECLARE(versatile, "arm,versatile-sysreg",
|
||||
versatile_sched_clock_init);
|
||||
|
|
|
|||
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