perf_events, x86: Implement intel core solo/duo support
Implement Intel Core Solo/Duo, aka. Intel Architectural Performance Monitoring Version 1. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Arjan van de Ven <arjan@linux.intel.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra
Ingo Molnar
Родитель
9717e6cd3d
Коммит
8c48e44419
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@ -227,6 +227,17 @@ static const u64 intel_perfmon_event_map[] =
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};
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static struct event_constraint intel_core_event_constraints[] =
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{
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
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INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_core2_event_constraints[] =
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{
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FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
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FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
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@ -1216,7 +1227,7 @@ static void intel_pmu_disable_all(void)
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intel_pmu_disable_bts();
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}
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static void amd_pmu_disable_all(void)
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static void x86_pmu_disable_all(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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int idx;
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@ -1226,11 +1237,11 @@ static void amd_pmu_disable_all(void)
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if (!test_bit(idx, cpuc->active_mask))
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continue;
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rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
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rdmsrl(x86_pmu.eventsel + idx, val);
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if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
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continue;
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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wrmsrl(x86_pmu.eventsel + idx, val);
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}
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}
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@ -1278,7 +1289,7 @@ static void intel_pmu_enable_all(void)
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}
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}
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static void amd_pmu_enable_all(void)
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static void x86_pmu_enable_all(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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int idx;
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@ -1292,7 +1303,7 @@ static void amd_pmu_enable_all(void)
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val = event->hw.config;
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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wrmsrl(x86_pmu.eventsel + idx, val);
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}
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}
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@ -1546,7 +1557,7 @@ static inline void intel_pmu_ack_status(u64 ack)
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wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
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}
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static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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{
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(void)checking_wrmsrl(hwc->config_base + idx,
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hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
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@ -1598,12 +1609,6 @@ intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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x86_pmu_disable_event(hwc, idx);
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}
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static inline void
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amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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{
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x86_pmu_disable_event(hwc, idx);
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}
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static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
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/*
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@ -1723,15 +1728,14 @@ static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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return;
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}
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x86_pmu_enable_event(hwc, idx);
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__x86_pmu_enable_event(hwc, idx);
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}
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static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (cpuc->enabled)
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x86_pmu_enable_event(hwc, idx);
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__x86_pmu_enable_event(hwc, idx);
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}
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/*
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@ -1988,50 +1992,6 @@ static void intel_pmu_reset(void)
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local_irq_restore(flags);
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}
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static int p6_pmu_handle_irq(struct pt_regs *regs)
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{
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struct perf_sample_data data;
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struct cpu_hw_events *cpuc;
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struct perf_event *event;
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struct hw_perf_event *hwc;
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int idx, handled = 0;
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u64 val;
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data.addr = 0;
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data.raw = NULL;
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cpuc = &__get_cpu_var(cpu_hw_events);
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for (idx = 0; idx < x86_pmu.num_events; idx++) {
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if (!test_bit(idx, cpuc->active_mask))
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continue;
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event = cpuc->events[idx];
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hwc = &event->hw;
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val = x86_perf_event_update(event, hwc, idx);
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if (val & (1ULL << (x86_pmu.event_bits - 1)))
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continue;
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/*
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* event overflow
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*/
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handled = 1;
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data.period = event->hw.last_period;
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if (!x86_perf_event_set_period(event, hwc, idx))
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continue;
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if (perf_event_overflow(event, 1, &data, regs))
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p6_pmu_disable_event(hwc, idx);
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}
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if (handled)
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inc_irq_stat(apic_perf_irqs);
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return handled;
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}
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/*
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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* rules apply:
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@ -2098,7 +2058,7 @@ again:
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return 1;
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}
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static int amd_pmu_handle_irq(struct pt_regs *regs)
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static int x86_pmu_handle_irq(struct pt_regs *regs)
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{
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struct perf_sample_data data;
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struct cpu_hw_events *cpuc;
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@ -2133,7 +2093,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs)
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continue;
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if (perf_event_overflow(event, 1, &data, regs))
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amd_pmu_disable_event(hwc, idx);
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x86_pmu.disable(hwc, idx);
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}
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if (handled)
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@ -2374,7 +2334,7 @@ static __read_mostly struct notifier_block perf_event_nmi_notifier = {
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static __initconst struct x86_pmu p6_pmu = {
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.name = "p6",
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.handle_irq = p6_pmu_handle_irq,
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.handle_irq = x86_pmu_handle_irq,
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.disable_all = p6_pmu_disable_all,
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.enable_all = p6_pmu_enable_all,
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.enable = p6_pmu_enable_event,
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@ -2401,6 +2361,29 @@ static __initconst struct x86_pmu p6_pmu = {
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.event_constraints = intel_p6_event_constraints
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};
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static __initconst struct x86_pmu core_pmu = {
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.name = "core",
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.handle_irq = x86_pmu_handle_irq,
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.disable_all = x86_pmu_disable_all,
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.enable_all = x86_pmu_enable_all,
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.enable = x86_pmu_enable_event,
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.disable = x86_pmu_disable_event,
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.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
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.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
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.event_map = intel_pmu_event_map,
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.raw_event = intel_pmu_raw_event,
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.max_events = ARRAY_SIZE(intel_perfmon_event_map),
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.apic = 1,
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/*
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* Intel PMCs cannot be accessed sanely above 32 bit width,
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* so we install an artificial 1<<31 period regardless of
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* the generic event period:
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*/
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.max_period = (1ULL << 31) - 1,
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.get_event_constraints = intel_get_event_constraints,
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.event_constraints = intel_core_event_constraints,
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};
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static __initconst struct x86_pmu intel_pmu = {
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.name = "Intel",
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.handle_irq = intel_pmu_handle_irq,
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@ -2427,11 +2410,11 @@ static __initconst struct x86_pmu intel_pmu = {
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static __initconst struct x86_pmu amd_pmu = {
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.name = "AMD",
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.handle_irq = amd_pmu_handle_irq,
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.disable_all = amd_pmu_disable_all,
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.enable_all = amd_pmu_enable_all,
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.enable = amd_pmu_enable_event,
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.disable = amd_pmu_disable_event,
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.handle_irq = x86_pmu_handle_irq,
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.disable_all = x86_pmu_disable_all,
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.enable_all = x86_pmu_enable_all,
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.enable = x86_pmu_enable_event,
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.disable = x86_pmu_disable_event,
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.eventsel = MSR_K7_EVNTSEL0,
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.perfctr = MSR_K7_PERFCTR0,
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.event_map = amd_pmu_event_map,
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@ -2498,9 +2481,10 @@ static __init int intel_pmu_init(void)
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version = eax.split.version_id;
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if (version < 2)
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return -ENODEV;
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x86_pmu = core_pmu;
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else
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x86_pmu = intel_pmu;
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x86_pmu = intel_pmu;
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x86_pmu.version = version;
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x86_pmu.num_events = eax.split.num_events;
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x86_pmu.event_bits = eax.split.bit_width;
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@ -2510,12 +2494,17 @@ static __init int intel_pmu_init(void)
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* Quirk: v2 perfmon does not report fixed-purpose events, so
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* assume at least 3 events:
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*/
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x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
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if (version > 1)
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x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
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/*
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* Install the hw-cache-events table:
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*/
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switch (boot_cpu_data.x86_model) {
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case 14: /* 65 nm core solo/duo, "Yonah" */
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pr_cont("Core events, ");
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break;
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case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
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case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
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case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
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@ -2523,7 +2512,7 @@ static __init int intel_pmu_init(void)
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memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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x86_pmu.event_constraints = intel_core_event_constraints;
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x86_pmu.event_constraints = intel_core2_event_constraints;
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pr_cont("Core2 events, ");
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break;
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