spi: Fixes for v4.17
A small collection of fixes accumilated since the merge window, all fairly small and driver specific. -----BEGIN PGP SIGNATURE----- iQFHBAABCgAxFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAlr+pAkTHGJyb29uaWVA a2VybmVsLm9yZwAKCRAk1otyXVSH0GwxB/98O1TEt6W/6wD5cy6c6RYkLK3RuK2Z dgMiWf+jQMmuw5kTFZxF5WhV+P06zgb43DX7+xWgJKzS9AqAuFtnbvMWK1FHoXIK 07/3OEXj1FbKupvO/lJLj2hVCrucPImLBru4dg9EoJ0bPSYs8VwyFpMZ8UQ9AOi7 8PV75jbsu8ReQ9Mt2NHN1mo9VW1d5lY42Hnm+ILqOESX76GmKy6lMtHvmkfkm4/P EgQdSPDTiycuWwzKQg72U5Jwe/NT4c9hND4Cst1HbXLdCAXawgEK8syR1RBj32+u QznZTiWUQ1TIVkcgwim5Mi6NqeQUHijbtsM8FjJ1olIkh7HeC4+y/lu6 =sghC -----END PGP SIGNATURE----- Merge tag 'spi-fix-v4.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A small collection of fixes accumilated since the merge window, all fairly small and driver specific" * tag 'spi-fix-v4.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: bcm2835aux: ensure interrupts are enabled for shared handler spi: bcm-qspi: Always read and set BSPI_MAST_N_BOOT_CTRL spi: bcm-qspi: Avoid setting MSPI_CDRAM_PCS for spi-nor master spi: pxa2xx: Allow 64-bit DMA spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo() spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR spi: imx: Update MODULE_DESCRIPTION to "SPI Controller driver"
This commit is contained in:
Коммит
8ccaecd014
|
@ -490,7 +490,7 @@ static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
|
||||||
|
|
||||||
static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
|
static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
|
||||||
{
|
{
|
||||||
if (!has_bspi(qspi) || (qspi->bspi_enabled))
|
if (!has_bspi(qspi))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
qspi->bspi_enabled = 1;
|
qspi->bspi_enabled = 1;
|
||||||
|
@ -505,7 +505,7 @@ static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
|
||||||
|
|
||||||
static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
|
static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
|
||||||
{
|
{
|
||||||
if (!has_bspi(qspi) || (!qspi->bspi_enabled))
|
if (!has_bspi(qspi))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
qspi->bspi_enabled = 0;
|
qspi->bspi_enabled = 0;
|
||||||
|
@ -519,16 +519,19 @@ static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
|
||||||
|
|
||||||
static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
|
static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
|
||||||
{
|
{
|
||||||
u32 data = 0;
|
u32 rd = 0;
|
||||||
|
u32 wr = 0;
|
||||||
|
|
||||||
if (qspi->curr_cs == cs)
|
|
||||||
return;
|
|
||||||
if (qspi->base[CHIP_SELECT]) {
|
if (qspi->base[CHIP_SELECT]) {
|
||||||
data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
|
rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
|
||||||
data = (data & ~0xff) | (1 << cs);
|
wr = (rd & ~0xff) | (1 << cs);
|
||||||
bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
|
if (rd == wr)
|
||||||
|
return;
|
||||||
|
bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
|
||||||
usleep_range(10, 20);
|
usleep_range(10, 20);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
|
||||||
qspi->curr_cs = cs;
|
qspi->curr_cs = cs;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -755,8 +758,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
|
||||||
dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
|
dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
|
||||||
}
|
}
|
||||||
mspi_cdram = MSPI_CDRAM_CONT_BIT;
|
mspi_cdram = MSPI_CDRAM_CONT_BIT;
|
||||||
mspi_cdram |= (~(1 << spi->chip_select) &
|
|
||||||
MSPI_CDRAM_PCS);
|
if (has_bspi(qspi))
|
||||||
|
mspi_cdram &= ~1;
|
||||||
|
else
|
||||||
|
mspi_cdram |= (~(1 << spi->chip_select) &
|
||||||
|
MSPI_CDRAM_PCS);
|
||||||
|
|
||||||
mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
|
mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
|
||||||
MSPI_CDRAM_BITSE_BIT);
|
MSPI_CDRAM_BITSE_BIT);
|
||||||
|
|
||||||
|
|
|
@ -184,6 +184,11 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
|
||||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||||
irqreturn_t ret = IRQ_NONE;
|
irqreturn_t ret = IRQ_NONE;
|
||||||
|
|
||||||
|
/* IRQ may be shared, so return if our interrupts are disabled */
|
||||||
|
if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
|
||||||
|
(BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
|
||||||
|
return ret;
|
||||||
|
|
||||||
/* check if we have data to read */
|
/* check if we have data to read */
|
||||||
while (bs->rx_len &&
|
while (bs->rx_len &&
|
||||||
(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
|
(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
|
||||||
|
|
|
@ -313,6 +313,14 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
|
||||||
|
|
||||||
while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
|
while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
|
||||||
(xspi->tx_bytes > 0)) {
|
(xspi->tx_bytes > 0)) {
|
||||||
|
|
||||||
|
/* When xspi in busy condition, bytes may send failed,
|
||||||
|
* then spi control did't work thoroughly, add one byte delay
|
||||||
|
*/
|
||||||
|
if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
|
||||||
|
CDNS_SPI_IXR_TXFULL)
|
||||||
|
usleep_range(10, 20);
|
||||||
|
|
||||||
if (xspi->txbuf)
|
if (xspi->txbuf)
|
||||||
cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
|
cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
|
||||||
else
|
else
|
||||||
|
|
|
@ -1701,7 +1701,7 @@ static struct platform_driver spi_imx_driver = {
|
||||||
};
|
};
|
||||||
module_platform_driver(spi_imx_driver);
|
module_platform_driver(spi_imx_driver);
|
||||||
|
|
||||||
MODULE_DESCRIPTION("SPI Master Controller driver");
|
MODULE_DESCRIPTION("SPI Controller driver");
|
||||||
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
|
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||||
|
|
|
@ -38,7 +38,7 @@ struct driver_data {
|
||||||
|
|
||||||
/* SSP register addresses */
|
/* SSP register addresses */
|
||||||
void __iomem *ioaddr;
|
void __iomem *ioaddr;
|
||||||
u32 ssdr_physical;
|
phys_addr_t ssdr_physical;
|
||||||
|
|
||||||
/* SSP masks*/
|
/* SSP masks*/
|
||||||
u32 dma_cr1;
|
u32 dma_cr1;
|
||||||
|
|
|
@ -283,6 +283,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
|
||||||
}
|
}
|
||||||
|
|
||||||
k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
|
k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
|
||||||
|
brps = min_t(int, brps, 32);
|
||||||
|
|
||||||
scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
|
scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
|
||||||
sh_msiof_write(p, TSCR, scr);
|
sh_msiof_write(p, TSCR, scr);
|
||||||
|
|
Загрузка…
Ссылка в новой задаче