Sudarsana Reddy Kalluru says:

====================
qed*: Support for NVM config attributes.

The patch series adds support for managing the NVM config attributes.
Patch (1) adds functionality to update config attributes via MFW.
Patch (2) adds driver interface for updating the config attributes.

Changes from previous versions:
-------------------------------
v4: Added more details on the functionality and its usage.
v3: Removed unused variable.
v2: Removed unused API.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-08-15 12:54:45 -07:00
Родитель 8714652fcd 0dabbe1bb3
Коммит 8ce2cfd42e
5 изменённых файлов: 138 добавлений и 0 удалений

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@ -12580,6 +12580,8 @@ struct public_drv_mb {
#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
#define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000
#define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000
#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
@ -12748,6 +12750,21 @@ struct public_drv_mb {
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF
#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16
#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17
#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18
#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19
#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
u32 fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000
#define FW_MSG_CODE_UNSUPPORTED 0x00000000

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@ -67,6 +67,8 @@
#define QED_ROCE_QPS (8192)
#define QED_ROCE_DPIS (8)
#define QED_RDMA_SRQS QED_ROCE_QPS
#define QED_NVM_CFG_SET_FLAGS 0xE
#define QED_NVM_CFG_SET_PF_FLAGS 0x1E
static char version[] =
"QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
@ -2231,6 +2233,69 @@ static int qed_nvm_flash_image_validate(struct qed_dev *cdev,
return 0;
}
/* Binary file format -
* /----------------------------------------------------------------------\
* 0B | 0x5 [command index] |
* 4B | Entity ID | Reserved | Number of config attributes |
* 8B | Config ID | Length | Value |
* | |
* \----------------------------------------------------------------------/
* There can be several cfg_id-Length-Value sets as specified by 'Number of...'.
* Entity ID - A non zero entity value for which the config need to be updated.
*
* The API parses config attributes from the user provided buffer and flashes
* them to the respective NVM path using Management FW inerface.
*/
static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data)
{
struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
u8 entity_id, len, buf[32];
struct qed_ptt *ptt;
u16 cfg_id, count;
int rc = 0, i;
u32 flags;
ptt = qed_ptt_acquire(hwfn);
if (!ptt)
return -EAGAIN;
/* NVM CFG ID attribute header */
*data += 4;
entity_id = **data;
*data += 2;
count = *((u16 *)*data);
*data += 2;
DP_VERBOSE(cdev, NETIF_MSG_DRV,
"Read config ids: entity id %02x num _attrs = %0d\n",
entity_id, count);
/* NVM CFG ID attributes */
for (i = 0; i < count; i++) {
cfg_id = *((u16 *)*data);
*data += 2;
len = **data;
(*data)++;
memcpy(buf, *data, len);
*data += len;
flags = entity_id ? QED_NVM_CFG_SET_PF_FLAGS :
QED_NVM_CFG_SET_FLAGS;
DP_VERBOSE(cdev, NETIF_MSG_DRV,
"cfg_id = %d len = %d\n", cfg_id, len);
rc = qed_mcp_nvm_set_cfg(hwfn, ptt, cfg_id, entity_id, flags,
buf, len);
if (rc) {
DP_ERR(cdev, "Error %d configuring %d\n", rc, cfg_id);
break;
}
}
qed_ptt_release(hwfn, ptt);
return rc;
}
static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
{
const struct firmware *image;
@ -2272,6 +2337,9 @@ static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
rc = qed_nvm_flash_image_access(cdev, &data,
&check_resp);
break;
case QED_NVM_FLASH_CMD_NVM_CFG_ID:
rc = qed_nvm_flash_cfg_write(cdev, &data);
break;
default:
DP_ERR(cdev, "Unknown command %08x\n", cmd_type);
rc = -EINVAL;

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@ -3750,3 +3750,35 @@ int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
return 0;
}
int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
u32 len)
{
u32 mb_param = 0, resp, param;
QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
if (flags & QED_NVM_CFG_OPTION_ALL)
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1);
if (flags & QED_NVM_CFG_OPTION_INIT)
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
if (flags & QED_NVM_CFG_OPTION_COMMIT)
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1);
if (flags & QED_NVM_CFG_OPTION_FREE)
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
entity_id);
}
return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_SET_NVM_CFG_OPTION,
mb_param, &resp, &param, len, (u32 *)p_buf);
}

Просмотреть файл

@ -251,6 +251,12 @@ union qed_mfw_tlv_data {
struct qed_mfw_tlv_iscsi iscsi;
};
#define QED_NVM_CFG_OPTION_ALL BIT(0)
#define QED_NVM_CFG_OPTION_INIT BIT(1)
#define QED_NVM_CFG_OPTION_COMMIT BIT(2)
#define QED_NVM_CFG_OPTION_FREE BIT(3)
#define QED_NVM_CFG_OPTION_ENTITY_SEL BIT(4)
/**
* @brief - returns the link params of the hw function
*
@ -1202,4 +1208,18 @@ int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
*/
int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
/**
* @brief Set NVM config attribute value.
*
* @param p_hwfn
* @param p_ptt
* @param option_id
* @param entity_id
* @param flags
* @param p_buf
* @param len
*/
int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
u32 len);
#endif

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@ -804,6 +804,7 @@ enum qed_nvm_flash_cmd {
QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
QED_NVM_FLASH_CMD_FILE_START = 0x3,
QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
QED_NVM_FLASH_CMD_NVM_MAX,
};