ARM: S5P: Move the SROM register definitions to plat-s5p
The SROM register difinitions of S5PV310/S5PC210 (mach/regs-srom.h) can be used to other S5P SoCs such as S5PV210/S5PC110. So moved into plat/regs-srom.h of plat-s5p directory. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
Родитель
387c31c7e5
Коммит
8cf460a5d7
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/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV310 - SROMC register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_SROM_H
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#define __ASM_ARCH_REGS_SROM_H __FILE__
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#include <mach/map.h>
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#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x))
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#define S5PV310_SROM_BW S5PV310_SROMREG(0x0)
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#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4)
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#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8)
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#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc)
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#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10)
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/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
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#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0
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#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1
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#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2
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#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3
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#define S5PV310_SROM_BW__CS_MASK 0xf
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#define S5PV310_SROM_BW__NCS0__SHIFT 0
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#define S5PV310_SROM_BW__NCS1__SHIFT 4
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#define S5PV310_SROM_BW__NCS2__SHIFT 8
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#define S5PV310_SROM_BW__NCS3__SHIFT 12
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/* applies to same to BCS0 - BCS3 */
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#define S5PV310_SROM_BCX__PMC__SHIFT 0
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#define S5PV310_SROM_BCX__TACP__SHIFT 4
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#define S5PV310_SROM_BCX__TCAH__SHIFT 8
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#define S5PV310_SROM_BCX__TCOH__SHIFT 12
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#define S5PV310_SROM_BCX__TACC__SHIFT 16
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#define S5PV310_SROM_BCX__TCOS__SHIFT 24
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#define S5PV310_SROM_BCX__TACS__SHIFT 28
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#endif /* __ASM_ARCH_REGS_SROM_H */
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@ -19,13 +19,13 @@
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#include <asm/mach-types.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-srom.h>
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#include <plat/s5pv310.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/sdhci.h>
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#include <mach/map.h>
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#include <mach/regs-srom.h>
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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@ -154,23 +154,22 @@ static void __init smdkc210_smsc911x_init(void)
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u32 cs1;
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/* configure nCS1 width to 16 bits */
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cs1 = __raw_readl(S5PV310_SROM_BW) &
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~(S5PV310_SROM_BW__CS_MASK <<
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S5PV310_SROM_BW__NCS1__SHIFT);
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cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
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(1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
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(1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
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S5PV310_SROM_BW__NCS1__SHIFT;
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__raw_writel(cs1, S5PV310_SROM_BW);
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cs1 = __raw_readl(S5P_SROM_BW) &
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~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
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cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
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(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
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(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
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S5P_SROM_BW__NCS1__SHIFT;
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__raw_writel(cs1, S5P_SROM_BW);
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/* set timing for nCS1 suitable for ethernet chip */
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__raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
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(0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
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(0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
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(0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
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(0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
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(0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
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(0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
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__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
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(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
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(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
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(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
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(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
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(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
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(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
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}
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static void __init smdkc210_map_io(void)
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@ -19,13 +19,13 @@
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#include <asm/mach-types.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-srom.h>
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#include <plat/s5pv310.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/sdhci.h>
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#include <mach/map.h>
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#include <mach/regs-srom.h>
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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@ -154,23 +154,22 @@ static void __init smdkv310_smsc911x_init(void)
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u32 cs1;
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/* configure nCS1 width to 16 bits */
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cs1 = __raw_readl(S5PV310_SROM_BW) &
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~(S5PV310_SROM_BW__CS_MASK <<
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S5PV310_SROM_BW__NCS1__SHIFT);
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cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
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(1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
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(1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
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S5PV310_SROM_BW__NCS1__SHIFT;
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__raw_writel(cs1, S5PV310_SROM_BW);
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cs1 = __raw_readl(S5P_SROM_BW) &
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~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
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cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
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(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
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(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
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S5P_SROM_BW__NCS1__SHIFT;
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__raw_writel(cs1, S5P_SROM_BW);
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/* set timing for nCS1 suitable for ethernet chip */
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__raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
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(0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
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(0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
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(0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
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(0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
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(0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
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(0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
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__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
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(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
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(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
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(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
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(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
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(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
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(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
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}
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static void __init smdkv310_map_io(void)
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@ -0,0 +1,50 @@
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/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P SROMC register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_S5P_REGS_SROM_H
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#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
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#include <mach/map.h>
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#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
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#define S5P_SROM_BW S5P_SROMREG(0x0)
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#define S5P_SROM_BC0 S5P_SROMREG(0x4)
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#define S5P_SROM_BC1 S5P_SROMREG(0x8)
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#define S5P_SROM_BC2 S5P_SROMREG(0xc)
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#define S5P_SROM_BC3 S5P_SROMREG(0x10)
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/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
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#define S5P_SROM_BW__DATAWIDTH__SHIFT 0
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#define S5P_SROM_BW__ADDRMODE__SHIFT 1
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#define S5P_SROM_BW__WAITENABLE__SHIFT 2
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#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
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#define S5P_SROM_BW__CS_MASK 0xf
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#define S5P_SROM_BW__NCS0__SHIFT 0
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#define S5P_SROM_BW__NCS1__SHIFT 4
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#define S5P_SROM_BW__NCS2__SHIFT 8
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#define S5P_SROM_BW__NCS3__SHIFT 12
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/* applies to same to BCS0 - BCS3 */
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#define S5P_SROM_BCX__PMC__SHIFT 0
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#define S5P_SROM_BCX__TACP__SHIFT 4
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#define S5P_SROM_BCX__TCAH__SHIFT 8
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#define S5P_SROM_BCX__TCOH__SHIFT 12
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#define S5P_SROM_BCX__TACC__SHIFT 16
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#define S5P_SROM_BCX__TCOS__SHIFT 24
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#define S5P_SROM_BCX__TACS__SHIFT 28
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#endif /* __ASM_PLAT_S5P_REGS_SROM_H */
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