qed*: Fix issues in the ptp filter config implementation.
PTP hardware filter configuration performed by the driver for a given
user requested config is not correct for some of the PTP modes.
Following changes are needed for PTP config-filter implementation.
1. NIG_REG_TX_PTP_EN register - Bits 0/1/2 respectively enables
TimeSync/"V1 frame format support"/"V2 frame format support" on
the TX side. Set the associated bits based on the user request.
2. ptp4l application fails to operate in Peer Delay mode. Following
changes are needed to fix this,
a. Driver should enable (set to 0) DA #1-related bits for IPv4,
IPv6 and MAC destination addresses in these registers:
NIG_REG_TX_LLH_PTP_RULE_MASK
NIG_REG_LLH_PTP_RULE_MASK
b. NIG_REG_LLH_PTP_PARAM_MASK/NIG_REG_TX_LLH_PTP_PARAM_MASK should
be set to 0x0 in all modes.
Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
sudarsana.kalluru@cavium.com
David S. Miller
Родитель
461eec1201
Коммит
8d3f87d8cd
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@ -188,39 +188,73 @@ static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles)
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}
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/* Filter PTP protocol packets that need to be timestamped */
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static int qed_ptp_hw_cfg_rx_filters(struct qed_dev *cdev,
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enum qed_ptp_filter_type type)
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static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
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enum qed_ptp_filter_type rx_type,
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enum qed_ptp_hwtstamp_tx_type tx_type)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 rule_mask, parm_mask;
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u32 rule_mask, enable_cfg = 0x0;
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switch (type) {
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case QED_PTP_FILTER_L2_IPV4_IPV6:
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parm_mask = 0x6AA;
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rule_mask = 0x3EEE;
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switch (rx_type) {
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case QED_PTP_FILTER_NONE:
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enable_cfg = 0x0;
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rule_mask = 0x3FFF;
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break;
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case QED_PTP_FILTER_L2:
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parm_mask = 0x6BF;
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case QED_PTP_FILTER_ALL:
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enable_cfg = 0x7;
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rule_mask = 0x3CAA;
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break;
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case QED_PTP_FILTER_V1_L4_EVENT:
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enable_cfg = 0x3;
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rule_mask = 0x3FFA;
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break;
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case QED_PTP_FILTER_V1_L4_GEN:
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enable_cfg = 0x3;
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rule_mask = 0x3FFE;
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break;
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case QED_PTP_FILTER_V2_L4_EVENT:
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enable_cfg = 0x5;
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rule_mask = 0x3FAA;
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break;
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case QED_PTP_FILTER_V2_L4_GEN:
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enable_cfg = 0x5;
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rule_mask = 0x3FEE;
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break;
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case QED_PTP_FILTER_V2_L2_EVENT:
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enable_cfg = 0x5;
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rule_mask = 0x3CFF;
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break;
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case QED_PTP_FILTER_V2_L2_GEN:
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enable_cfg = 0x5;
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rule_mask = 0x3EFF;
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break;
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case QED_PTP_FILTER_IPV4_IPV6:
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parm_mask = 0x7EA;
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rule_mask = 0x3FFE;
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case QED_PTP_FILTER_V2_EVENT:
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enable_cfg = 0x5;
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rule_mask = 0x3CAA;
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break;
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case QED_PTP_FILTER_IPV4:
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parm_mask = 0x7EE;
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rule_mask = 0x3FFE;
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case QED_PTP_FILTER_V2_GEN:
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enable_cfg = 0x5;
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rule_mask = 0x3EEE;
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break;
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default:
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DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", type);
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DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", rx_type);
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return -EINVAL;
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}
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, parm_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, enable_cfg);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_TO_HOST, 0x1);
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if (tx_type == QED_PTP_HWTSTAMP_TX_OFF) {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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} else {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, enable_cfg);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, rule_mask);
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}
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/* Reset possibly old timestamps */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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@ -383,17 +417,6 @@ static int qed_ptp_hw_enable(struct qed_dev *cdev)
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return 0;
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}
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static int qed_ptp_hw_hwtstamp_tx_on(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x6AA);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3EEE);
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return 0;
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}
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static int qed_ptp_hw_disable(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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@ -419,8 +442,7 @@ static int qed_ptp_hw_disable(struct qed_dev *cdev)
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}
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const struct qed_eth_ptp_ops qed_ptp_ops_pass = {
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.hwtstamp_tx_on = qed_ptp_hw_hwtstamp_tx_on,
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.cfg_rx_filters = qed_ptp_hw_cfg_rx_filters,
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.cfg_filters = qed_ptp_hw_cfg_filters,
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.read_rx_ts = qed_ptp_hw_read_rx_ts,
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.read_tx_ts = qed_ptp_hw_read_tx_ts,
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.read_cc = qed_ptp_hw_read_cc,
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@ -209,6 +209,8 @@ static u64 qede_ptp_read_cc(const struct cyclecounter *cc)
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static int qede_ptp_cfg_filters(struct qede_dev *edev)
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{
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enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON;
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enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE;
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struct qede_ptp *ptp = edev->ptp;
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if (!ptp)
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@ -222,7 +224,12 @@ static int qede_ptp_cfg_filters(struct qede_dev *edev)
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switch (ptp->tx_type) {
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case HWTSTAMP_TX_ON:
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edev->flags |= QEDE_TX_TIMESTAMPING_EN;
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ptp->ops->hwtstamp_tx_on(edev->cdev);
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tx_type = QED_PTP_HWTSTAMP_TX_ON;
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break;
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case HWTSTAMP_TX_OFF:
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edev->flags &= ~QEDE_TX_TIMESTAMPING_EN;
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tx_type = QED_PTP_HWTSTAMP_TX_OFF;
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break;
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case HWTSTAMP_TX_ONESTEP_SYNC:
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@ -233,42 +240,57 @@ static int qede_ptp_cfg_filters(struct qede_dev *edev)
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spin_lock_bh(&ptp->lock);
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switch (ptp->rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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rx_filter = QED_PTP_FILTER_NONE;
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break;
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case HWTSTAMP_FILTER_ALL:
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case HWTSTAMP_FILTER_SOME:
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ptp->rx_filter = HWTSTAMP_FILTER_NONE;
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rx_filter = QED_PTP_FILTER_ALL;
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
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rx_filter = QED_PTP_FILTER_V1_L4_EVENT;
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
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/* Initialize PTP detection for UDP/IPv4 events */
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ptp->ops->cfg_rx_filters(edev->cdev, QED_PTP_FILTER_IPV4);
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rx_filter = QED_PTP_FILTER_V1_L4_GEN;
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break;
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case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
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rx_filter = QED_PTP_FILTER_V2_L4_EVENT;
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break;
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case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
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/* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
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ptp->ops->cfg_rx_filters(edev->cdev, QED_PTP_FILTER_IPV4_IPV6);
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rx_filter = QED_PTP_FILTER_V2_L4_GEN;
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break;
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case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
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rx_filter = QED_PTP_FILTER_V2_L2_EVENT;
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break;
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case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
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/* Initialize PTP detection L2 events */
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ptp->ops->cfg_rx_filters(edev->cdev, QED_PTP_FILTER_L2);
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rx_filter = QED_PTP_FILTER_V2_L2_GEN;
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break;
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case HWTSTAMP_FILTER_PTP_V2_EVENT:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
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rx_filter = QED_PTP_FILTER_V2_EVENT;
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break;
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
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/* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
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ptp->ops->cfg_rx_filters(edev->cdev,
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QED_PTP_FILTER_L2_IPV4_IPV6);
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rx_filter = QED_PTP_FILTER_V2_GEN;
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break;
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}
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ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type);
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spin_unlock_bh(&ptp->lock);
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return 0;
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@ -164,10 +164,21 @@ struct qed_eth_cb_ops {
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#define QED_MAX_PHC_DRIFT_PPB 291666666
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enum qed_ptp_filter_type {
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QED_PTP_FILTER_L2,
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QED_PTP_FILTER_IPV4,
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QED_PTP_FILTER_IPV4_IPV6,
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QED_PTP_FILTER_L2_IPV4_IPV6
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QED_PTP_FILTER_NONE,
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QED_PTP_FILTER_ALL,
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QED_PTP_FILTER_V1_L4_EVENT,
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QED_PTP_FILTER_V1_L4_GEN,
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QED_PTP_FILTER_V2_L4_EVENT,
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QED_PTP_FILTER_V2_L4_GEN,
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QED_PTP_FILTER_V2_L2_EVENT,
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QED_PTP_FILTER_V2_L2_GEN,
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QED_PTP_FILTER_V2_EVENT,
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QED_PTP_FILTER_V2_GEN
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};
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enum qed_ptp_hwtstamp_tx_type {
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QED_PTP_HWTSTAMP_TX_OFF,
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QED_PTP_HWTSTAMP_TX_ON,
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};
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#ifdef CONFIG_DCB
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@ -230,8 +241,8 @@ struct qed_eth_dcbnl_ops {
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#endif
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struct qed_eth_ptp_ops {
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int (*hwtstamp_tx_on)(struct qed_dev *);
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int (*cfg_rx_filters)(struct qed_dev *, enum qed_ptp_filter_type);
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int (*cfg_filters)(struct qed_dev *, enum qed_ptp_filter_type,
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enum qed_ptp_hwtstamp_tx_type);
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int (*read_rx_ts)(struct qed_dev *, u64 *);
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int (*read_tx_ts)(struct qed_dev *, u64 *);
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int (*read_cc)(struct qed_dev *, u64 *);
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