clk: at91: clk-master: remove dead code
Commitfacb87ad75("clk: at91: sama7g5: remove prescaler part of master clock") removed the master clock's prescaler from clock tree of SAMA7G5 as it has been discovered that there is a hardware bug when trying to change it at run-time (bug is described in description of commitfacb87ad75("clk: at91: sama7g5: remove prescaler part of master clock")). This was previously changed at CPUFreq driver request. Thus, with commitfacb87ad75("clk: at91: sama7g5: remove prescaler part of master clock") there is no need of code that handles run-time changes of master clock's prescaler, thus remove this code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea
Nicolas Ferre
Родитель
1a944729d8
Коммит
8e842f02af
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@ -143,8 +143,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
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parent_names,
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&at91rm9200_master_layout,
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&rm9200_mck_characteristics,
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&rm9200_mck_lock, CLK_SET_RATE_GATE,
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INT_MIN);
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&rm9200_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -419,8 +419,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
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parent_names,
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&at91rm9200_master_layout,
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data->mck_characteristics,
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&at91sam9260_mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&at91sam9260_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -154,8 +154,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
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parent_names,
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&at91rm9200_master_layout,
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&mck_characteristics,
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&at91sam9g45_mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&at91sam9g45_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -181,8 +181,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
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parent_names,
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&at91sam9x5_master_layout,
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&mck_characteristics,
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&at91sam9n12_mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&at91sam9n12_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -123,8 +123,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
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parent_names,
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&at91rm9200_master_layout,
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&sam9rl_mck_characteristics,
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&sam9rl_mck_lock, CLK_SET_RATE_GATE,
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INT_MIN);
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&sam9rl_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -201,8 +201,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91sam9x5_master_layout,
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&mck_characteristics, &mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&mck_characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -374,85 +374,6 @@ static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
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}
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}
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static int clk_master_pres_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_master *master = to_clk_master(hw);
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struct clk_rate_request req_parent = *req;
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const struct clk_master_characteristics *characteristics =
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master->characteristics;
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struct clk_hw *parent;
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long best_rate = LONG_MIN, best_diff = LONG_MIN;
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u32 pres;
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int i;
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if (master->chg_pid < 0)
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return -EOPNOTSUPP;
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parent = clk_hw_get_parent_by_index(hw, master->chg_pid);
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if (!parent)
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return -EOPNOTSUPP;
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for (i = 0; i <= MASTER_PRES_MAX; i++) {
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if (characteristics->have_div3_pres && i == MASTER_PRES_MAX)
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pres = 3;
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else
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pres = 1 << i;
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req_parent.rate = req->rate * pres;
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if (__clk_determine_rate(parent, &req_parent))
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continue;
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clk_sama7g5_master_best_diff(req, parent, req_parent.rate,
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&best_diff, &best_rate, pres);
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if (!best_diff)
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break;
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}
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return 0;
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}
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static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_master *master = to_clk_master(hw);
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unsigned long flags;
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unsigned int pres, mckr, tmp;
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int ret;
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pres = DIV_ROUND_CLOSEST(parent_rate, rate);
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if (pres > MASTER_PRES_MAX)
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return -EINVAL;
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else if (pres == 3)
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pres = MASTER_PRES_MAX;
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else if (pres)
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pres = ffs(pres) - 1;
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spin_lock_irqsave(master->lock, flags);
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ret = regmap_read(master->regmap, master->layout->offset, &mckr);
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if (ret)
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goto unlock;
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mckr &= master->layout->mask;
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tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;
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if (pres == tmp)
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goto unlock;
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mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);
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mckr |= (pres << master->layout->pres_shift);
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ret = regmap_write(master->regmap, master->layout->offset, mckr);
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if (ret)
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goto unlock;
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while (!clk_master_ready(master))
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cpu_relax();
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unlock:
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spin_unlock_irqrestore(master->lock, flags);
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return ret;
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}
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static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -539,13 +460,6 @@ static void clk_master_pres_restore_context(struct clk_hw *hw)
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pr_warn("MCKR PRES was not configured properly by firmware!\n");
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}
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static void clk_master_pres_restore_context_chg(struct clk_hw *hw)
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{
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struct clk_master *master = to_clk_master(hw);
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clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);
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}
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static const struct clk_ops master_pres_ops = {
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.prepare = clk_master_prepare,
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.is_prepared = clk_master_is_prepared,
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@ -555,25 +469,13 @@ static const struct clk_ops master_pres_ops = {
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.restore_context = clk_master_pres_restore_context,
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};
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static const struct clk_ops master_pres_ops_chg = {
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.prepare = clk_master_prepare,
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.is_prepared = clk_master_is_prepared,
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.determine_rate = clk_master_pres_determine_rate,
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.recalc_rate = clk_master_pres_recalc_rate,
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.get_parent = clk_master_pres_get_parent,
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.set_rate = clk_master_pres_set_rate,
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.save_context = clk_master_pres_save_context,
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.restore_context = clk_master_pres_restore_context_chg,
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};
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static struct clk_hw * __init
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at91_clk_register_master_internal(struct regmap *regmap,
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const char *name, int num_parents,
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const char **parent_names,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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const struct clk_ops *ops, spinlock_t *lock, u32 flags,
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int chg_pid)
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const struct clk_ops *ops, spinlock_t *lock, u32 flags)
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{
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struct clk_master *master;
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struct clk_init_data init;
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@ -599,7 +501,6 @@ at91_clk_register_master_internal(struct regmap *regmap,
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master->layout = layout;
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master->characteristics = characteristics;
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master->regmap = regmap;
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master->chg_pid = chg_pid;
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master->lock = lock;
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if (ops == &master_div_ops_chg) {
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@ -628,19 +529,13 @@ at91_clk_register_master_pres(struct regmap *regmap,
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const char **parent_names,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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spinlock_t *lock, u32 flags, int chg_pid)
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spinlock_t *lock)
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{
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const struct clk_ops *ops;
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if (flags & CLK_SET_RATE_GATE)
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ops = &master_pres_ops;
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else
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ops = &master_pres_ops_chg;
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return at91_clk_register_master_internal(regmap, name, num_parents,
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parent_names, layout,
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characteristics, ops,
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lock, flags, chg_pid);
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characteristics,
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&master_pres_ops,
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lock, CLK_SET_RATE_GATE);
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}
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struct clk_hw * __init
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@ -661,7 +556,7 @@ at91_clk_register_master_div(struct regmap *regmap,
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hw = at91_clk_register_master_internal(regmap, name, 1,
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&parent_name, layout,
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characteristics, ops,
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lock, flags, -EINVAL);
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lock, flags);
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if (!IS_ERR(hw) && safe_div) {
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master_div = to_clk_master(hw);
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@ -392,8 +392,7 @@ of_at91_clk_master_setup(struct device_node *np,
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
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parent_names, layout,
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characteristics, &mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto out_free_characteristics;
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@ -175,7 +175,7 @@ at91_clk_register_master_pres(struct regmap *regmap, const char *name,
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int num_parents, const char **parent_names,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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spinlock_t *lock, u32 flags, int chg_pid);
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spinlock_t *lock);
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struct clk_hw * __init
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at91_clk_register_master_div(struct regmap *regmap, const char *name,
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@ -271,8 +271,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
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parent_names[2] = "pllack_divck";
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3,
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parent_names, &sam9x60_master_layout,
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&mck_characteristics, &mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&mck_characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -242,8 +242,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91sam9x5_master_layout,
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&mck_characteristics, &mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&mck_characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -175,8 +175,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91sam9x5_master_layout,
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&mck_characteristics, &mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&mck_characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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@ -190,8 +190,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91sam9x5_master_layout,
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&mck_characteristics, &mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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&mck_characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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