arm64: mm: ensure patched kernel text is fetched from PoU
The arm64 booting document requires that the bootloader has cleaned the kernel image to the PoC. However, when a CPU re-enters the kernel due to either a CPU hotplug "on" event or resuming from a low-power state (e.g. cpuidle), the kernel text may in-fact be dirty at the PoU due to things like alternative patching or even module loading. Thanks to I-cache speculation with the MMU off, stale instructions could be fetched prior to enabling the MMU, potentially leading to crashes when executing regions of code that have been modified at runtime. This patch addresses the issue by ensuring that the local I-cache is invalidated immediately after a CPU has enabled its MMU but before jumping out of the identity mapping. Any stale instructions fetched from the PoC will then be discarded and refetched correctly from the PoU. Patching kernel text executed prior to the MMU being enabled is prohibited, so the early entry code will always be clean. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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8ec4198743
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@ -634,5 +634,13 @@ __enable_mmu:
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isb
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msr sctlr_el1, x0
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isb
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/*
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* Invalidate the local I-cache so that any instructions fetched
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* speculatively from the PoC are discarded, since they may have
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* been dynamically patched at the PoU.
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*/
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ic iallu
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dsb nsh
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isb
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br x27
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ENDPROC(__enable_mmu)
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@ -133,6 +133,14 @@ ENTRY(cpu_resume_mmu)
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ldr x3, =cpu_resume_after_mmu
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msr sctlr_el1, x0 // restore sctlr_el1
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isb
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/*
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* Invalidate the local I-cache so that any instructions fetched
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* speculatively from the PoC are discarded, since they may have
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* been dynamically patched at the PoU.
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*/
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ic iallu
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dsb nsh
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isb
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br x3 // global jump to virtual address
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ENDPROC(cpu_resume_mmu)
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.popsection
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@ -146,7 +146,6 @@ ENDPROC(cpu_do_switch_mm)
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* value of the SCTLR_EL1 register.
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*/
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ENTRY(__cpu_setup)
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ic iallu // I+BTB cache invalidate
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tlbi vmalle1is // invalidate I + D TLBs
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dsb ish
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