Documentation: Add SoundWire summary
SoundWire is a new Linux bus which implements a new MIPI bus protocol 'SoundWire'. The summary of SoundWire bus and API is documented in the 'summary' file. Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com> Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Acked-By: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Sanyog Kale
Greg Kroah-Hartman
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Коммит
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@ -48,6 +48,7 @@ available subsections can be seen below.
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misc_devices
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misc_devices
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dmaengine/index
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dmaengine/index
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slimbus
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slimbus
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soundwire/index
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.. only:: subproject and html
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.. only:: subproject and html
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@ -0,0 +1,15 @@
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=======================
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SoundWire Documentation
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=======================
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.. toctree::
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:maxdepth: 1
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summary
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.. only:: subproject
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Indices
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=======
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* :ref:`genindex`
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@ -0,0 +1,207 @@
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===========================
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SoundWire Subsystem Summary
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===========================
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SoundWire is a new interface ratified in 2015 by the MIPI Alliance.
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SoundWire is used for transporting data typically related to audio
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functions. SoundWire interface is optimized to integrate audio devices in
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mobile or mobile inspired systems.
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SoundWire is a 2-pin multi-drop interface with data and clock line. It
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facilitates development of low cost, efficient, high performance systems.
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Broad level key features of SoundWire interface include:
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(1) Transporting all of payload data channels, control information, and setup
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commands over a single two-pin interface.
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(2) Lower clock frequency, and hence lower power consumption, by use of DDR
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(Dual Data Rate) data transmission.
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(3) Clock scaling and optional multiple data lanes to give wide flexibility
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in data rate to match system requirements.
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(4) Device status monitoring, including interrupt-style alerts to the Master.
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The SoundWire protocol supports up to eleven Slave interfaces. All the
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interfaces share the common Bus containing data and clock line. Each of the
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Slaves can support up to 14 Data Ports. 13 Data Ports are dedicated to audio
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transport. Data Port0 is dedicated to transport of Bulk control information,
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each of the audio Data Ports (1..14) can support up to 8 Channels in
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transmit or receiving mode (typically fixed direction but configurable
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direction is enabled by the specification). Bandwidth restrictions to
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~19.2..24.576Mbits/s don't however allow for 11*13*8 channels to be
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transmitted simultaneously.
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Below figure shows an example of connectivity between a SoundWire Master and
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two Slave devices. ::
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+---------------+ +---------------+
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| | Clock Signal | |
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| Master |-------+-------------------------------| Slave |
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| Interface | | Data Signal | Interface 1 |
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| |-------|-------+-----------------------| |
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+---------------+ | | +---------------+
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+--+-------+--+
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| Slave |
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| Interface 2 |
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+-------------+
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Terminology
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===========
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The MIPI SoundWire specification uses the term 'device' to refer to a Master
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or Slave interface, which of course can be confusing. In this summary and
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code we use the term interface only to refer to the hardware. We follow the
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Linux device model by mapping each Slave interface connected on the bus as a
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device managed by a specific driver. The Linux SoundWire subsystem provides
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a framework to implement a SoundWire Slave driver with an API allowing
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3rd-party vendors to enable implementation-defined functionality while
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common setup/configuration tasks are handled by the bus.
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Bus:
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Implements SoundWire Linux Bus which handles the SoundWire protocol.
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Programs all the MIPI-defined Slave registers. Represents a SoundWire
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Master. Multiple instances of Bus may be present in a system.
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Slave:
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Registers as SoundWire Slave device (Linux Device). Multiple Slave devices
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can register to a Bus instance.
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Slave driver:
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Driver controlling the Slave device. MIPI-specified registers are controlled
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directly by the Bus (and transmitted through the Master driver/interface).
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Any implementation-defined Slave register is controlled by Slave driver. In
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practice, it is expected that the Slave driver relies on regmap and does not
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request direct register access.
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Programming interfaces (SoundWire Master interface Driver)
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==========================================================
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SoundWire Bus supports programming interfaces for the SoundWire Master
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implementation and SoundWire Slave devices. All the code uses the "sdw"
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prefix commonly used by SoC designers and 3rd party vendors.
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Each of the SoundWire Master interfaces needs to be registered to the Bus.
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Bus implements API to read standard Master MIPI properties and also provides
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callback in Master ops for Master driver to implement its own functions that
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provides capabilities information. DT support is not implemented at this
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time but should be trivial to add since capabilities are enabled with the
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``device_property_`` API.
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The Master interface along with the Master interface capabilities are
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registered based on board file, DT or ACPI.
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Following is the Bus API to register the SoundWire Bus:
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.. code-block:: c
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int sdw_add_bus_master(struct sdw_bus *bus)
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{
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if (!bus->dev)
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return -ENODEV;
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mutex_init(&bus->lock);
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INIT_LIST_HEAD(&bus->slaves);
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/* Check ACPI for Slave devices */
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sdw_acpi_find_slaves(bus);
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/* Check DT for Slave devices */
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sdw_of_find_slaves(bus);
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return 0;
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}
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This will initialize sdw_bus object for Master device. "sdw_master_ops" and
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"sdw_master_port_ops" callback functions are provided to the Bus.
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"sdw_master_ops" is used by Bus to control the Bus in the hardware specific
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way. It includes Bus control functions such as sending the SoundWire
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read/write messages on Bus, setting up clock frequency & Stream
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Synchronization Point (SSP). The "sdw_master_ops" structure abstracts the
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hardware details of the Master from the Bus.
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"sdw_master_port_ops" is used by Bus to setup the Port parameters of the
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Master interface Port. Master interface Port register map is not defined by
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MIPI specification, so Bus calls the "sdw_master_port_ops" callback
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function to do Port operations like "Port Prepare", "Port Transport params
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set", "Port enable and disable". The implementation of the Master driver can
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then perform hardware-specific configurations.
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Programming interfaces (SoundWire Slave Driver)
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===============================================
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The MIPI specification requires each Slave interface to expose a unique
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48-bit identifier, stored in 6 read-only dev_id registers. This dev_id
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identifier contains vendor and part information, as well as a field enabling
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to differentiate between identical components. An additional class field is
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currently unused. Slave driver is written for a specific vendor and part
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identifier, Bus enumerates the Slave device based on these two ids.
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Slave device and driver match is done based on these two ids . Probe
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of the Slave driver is called by Bus on successful match between device and
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driver id. A parent/child relationship is enforced between Master and Slave
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devices (the logical representation is aligned with the physical
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connectivity).
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The information on Master/Slave dependencies is stored in platform data,
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board-file, ACPI or DT. The MIPI Software specification defines additional
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link_id parameters for controllers that have multiple Master interfaces. The
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dev_id registers are only unique in the scope of a link, and the link_id
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unique in the scope of a controller. Both dev_id and link_id are not
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necessarily unique at the system level but the parent/child information is
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used to avoid ambiguity.
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.. code-block:: c
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static const struct sdw_device_id slave_id[] = {
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SDW_SLAVE_ENTRY(0x025d, 0x700, 0),
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{},
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};
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MODULE_DEVICE_TABLE(sdw, slave_id);
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static struct sdw_driver slave_sdw_driver = {
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.driver = {
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.name = "slave_xxx",
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.pm = &slave_runtime_pm,
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},
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.probe = slave_sdw_probe,
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.remove = slave_sdw_remove,
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.ops = &slave_slave_ops,
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.id_table = slave_id,
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};
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For capabilities, Bus implements API to read standard Slave MIPI properties
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and also provides callback in Slave ops for Slave driver to implement own
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function that provides capabilities information. Bus needs to know a set of
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Slave capabilities to program Slave registers and to control the Bus
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reconfigurations.
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Future enhancements to be done
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==============================
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(1) Bulk Register Access (BRA) transfers.
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(2) Multiple data lane support.
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Links
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=====
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SoundWire MIPI specification 1.1 is available at:
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https://members.mipi.org/wg/All-Members/document/70290
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SoundWire MIPI DisCo (Discovery and Configuration) specification is
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available at:
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https://www.mipi.org/specifications/mipi-disco-soundwire
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(publicly accessible with registration or directly accessible to MIPI
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members)
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MIPI Alliance Manufacturer ID Page: mid.mipi.org
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