RTC: DaVinci RTC driver
This driver features: * Alarm support. * Periodic interrupt by using a timer include into the RTC module. * The update interrupt is not supported by this RTC module. This driver was tested on a DM365 EVM by using the rtc-test application from the Documentation/rtc.txt. Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Alessandro Zummo <a.zummo@towertech.it>
This commit is contained in:
Miguel Aguilar
Kevin Hilman
Родитель
a7e05065f5
Коммит
8ecf6c54d4
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@ -620,6 +620,16 @@ config RTC_DRV_NUC900
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comment "on-CPU RTC drivers"
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config RTC_DRV_DAVINCI
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tristate "TI DaVinci RTC"
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depends on ARCH_DAVINCI_DM365
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help
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If you say yes here you get support for the RTC on the
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DaVinci platforms (DM365).
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This driver can also be built as a module. If so, the module
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will be called rtc-davinci.
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config RTC_DRV_OMAP
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tristate "TI OMAP1"
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depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
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@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
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obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
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obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
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obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
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obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
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obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
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obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
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obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
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@ -0,0 +1,673 @@
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/*
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* DaVinci Power Management and Real Time Clock Driver for TI platforms
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*
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* Copyright (C) 2009 Texas Instruments, Inc
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*
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* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/rtc.h>
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#include <linux/bcd.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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/*
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* The DaVinci RTC is a simple RTC with the following
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* Sec: 0 - 59 : BCD count
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* Min: 0 - 59 : BCD count
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* Hour: 0 - 23 : BCD count
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* Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
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*/
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/* PRTC interface registers */
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#define DAVINCI_PRTCIF_PID 0x00
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#define PRTCIF_CTLR 0x04
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#define PRTCIF_LDATA 0x08
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#define PRTCIF_UDATA 0x0C
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#define PRTCIF_INTEN 0x10
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#define PRTCIF_INTFLG 0x14
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/* PRTCIF_CTLR bit fields */
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#define PRTCIF_CTLR_BUSY BIT(31)
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#define PRTCIF_CTLR_SIZE BIT(25)
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#define PRTCIF_CTLR_DIR BIT(24)
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#define PRTCIF_CTLR_BENU_MSB BIT(23)
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#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
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#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
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#define PRTCIF_CTLR_BENU_LSB BIT(20)
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#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
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#define PRTCIF_CTLR_BENL_MSB BIT(19)
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#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
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#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
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#define PRTCIF_CTLR_BENL_LSB BIT(16)
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#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
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/* PRTCIF_INTEN bit fields */
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#define PRTCIF_INTEN_RTCSS BIT(1)
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#define PRTCIF_INTEN_RTCIF BIT(0)
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#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
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| PRTCIF_INTEN_RTCIF)
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/* PRTCIF_INTFLG bit fields */
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#define PRTCIF_INTFLG_RTCSS BIT(1)
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#define PRTCIF_INTFLG_RTCIF BIT(0)
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#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
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| PRTCIF_INTFLG_RTCIF)
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/* PRTC subsystem registers */
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#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
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#define PRTCSS_RTC_CTRL (0x10)
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#define PRTCSS_RTC_WDT (0x11)
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#define PRTCSS_RTC_TMR0 (0x12)
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#define PRTCSS_RTC_TMR1 (0x13)
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#define PRTCSS_RTC_CCTRL (0x14)
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#define PRTCSS_RTC_SEC (0x15)
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#define PRTCSS_RTC_MIN (0x16)
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#define PRTCSS_RTC_HOUR (0x17)
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#define PRTCSS_RTC_DAY0 (0x18)
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#define PRTCSS_RTC_DAY1 (0x19)
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#define PRTCSS_RTC_AMIN (0x1A)
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#define PRTCSS_RTC_AHOUR (0x1B)
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#define PRTCSS_RTC_ADAY0 (0x1C)
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#define PRTCSS_RTC_ADAY1 (0x1D)
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#define PRTCSS_RTC_CLKC_CNT (0x20)
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/* PRTCSS_RTC_INTC_EXTENA1 */
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#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
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/* PRTCSS_RTC_CTRL bit fields */
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#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
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#define PRTCSS_RTC_CTRL_WEN BIT(6)
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#define PRTCSS_RTC_CTRL_WDRT BIT(5)
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#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
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#define PRTCSS_RTC_CTRL_TE BIT(3)
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#define PRTCSS_RTC_CTRL_TIEN BIT(2)
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#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
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#define PRTCSS_RTC_CTRL_TMMD BIT(0)
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/* PRTCSS_RTC_CCTRL bit fields */
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#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
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#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
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#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
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#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
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#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
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#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
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#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
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static DEFINE_SPINLOCK(davinci_rtc_lock);
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struct davinci_rtc {
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struct rtc_device *rtc;
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void __iomem *base;
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resource_size_t pbase;
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size_t base_size;
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int irq;
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};
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static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
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u32 val, u32 addr)
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{
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writel(val, davinci_rtc->base + addr);
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}
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static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
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{
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return readl(davinci_rtc->base + addr);
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}
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static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
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{
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while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
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cpu_relax();
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}
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static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
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unsigned long val, u8 addr)
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{
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rtcif_wait(davinci_rtc);
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rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
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rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
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rtcif_wait(davinci_rtc);
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}
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static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
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{
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rtcif_wait(davinci_rtc);
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rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
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PRTCIF_CTLR);
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rtcif_wait(davinci_rtc);
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return rtcif_read(davinci_rtc, PRTCIF_LDATA);
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}
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static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
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{
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while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
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PRTCSS_RTC_CCTRL_CALBUSY)
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cpu_relax();
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}
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static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
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{
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struct davinci_rtc *davinci_rtc = class_dev;
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unsigned long events = 0;
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u32 irq_flg;
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u8 alm_irq, tmr_irq;
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u8 rtc_ctrl, rtc_cctrl;
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int ret = IRQ_NONE;
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irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
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PRTCIF_INTFLG_RTCSS;
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alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
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PRTCSS_RTC_CCTRL_ALMFLG;
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tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
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PRTCSS_RTC_CTRL_TMRFLG;
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if (irq_flg) {
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if (alm_irq) {
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events |= RTC_IRQF | RTC_AF;
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rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
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rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
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rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
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} else if (tmr_irq) {
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events |= RTC_IRQF | RTC_PF;
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rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
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rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
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rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
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}
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rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
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PRTCIF_INTFLG);
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rtc_update_irq(davinci_rtc->rtc, 1, events);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static int
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davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u8 rtc_ctrl;
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
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switch (cmd) {
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case RTC_WIE_ON:
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rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
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break;
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case RTC_WIE_OFF:
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rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
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break;
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case RTC_UIE_OFF:
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case RTC_UIE_ON:
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ret = -ENOTTY;
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break;
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default:
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ret = -ENOIOCTLCMD;
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}
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rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return ret;
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}
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static int convertfromdays(u16 days, struct rtc_time *tm)
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{
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int tmp_days, year, mon;
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for (year = 2000;; year++) {
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tmp_days = rtc_year_days(1, 12, year);
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if (days >= tmp_days)
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days -= tmp_days;
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else {
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for (mon = 0;; mon++) {
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tmp_days = rtc_month_days(mon, year);
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if (days >= tmp_days) {
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days -= tmp_days;
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} else {
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tm->tm_year = year - 1900;
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tm->tm_mon = mon;
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tm->tm_mday = days + 1;
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break;
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}
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}
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break;
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}
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}
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return 0;
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}
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static int convert2days(u16 *days, struct rtc_time *tm)
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{
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int i;
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*days = 0;
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/* epoch == 1900 */
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if (tm->tm_year < 100 || tm->tm_year > 199)
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return -EINVAL;
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for (i = 2000; i < 1900 + tm->tm_year; i++)
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*days += rtc_year_days(1, 12, i);
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*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
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return 0;
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}
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static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u16 days = 0;
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u8 day0, day1;
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unsigned long flags;
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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davinci_rtcss_calendar_wait(davinci_rtc);
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tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
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davinci_rtcss_calendar_wait(davinci_rtc);
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tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
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davinci_rtcss_calendar_wait(davinci_rtc);
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tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
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davinci_rtcss_calendar_wait(davinci_rtc);
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day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
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davinci_rtcss_calendar_wait(davinci_rtc);
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day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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days |= day1;
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days <<= 8;
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days |= day0;
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if (convertfromdays(days, tm) < 0)
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return -EINVAL;
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return 0;
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}
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static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u16 days;
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u8 rtc_cctrl;
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unsigned long flags;
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if (convert2days(&days, tm) < 0)
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return -EINVAL;
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
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rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
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rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
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rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return 0;
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}
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static int davinci_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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unsigned long flags;
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u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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if (enabled)
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rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
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PRTCSS_RTC_CCTRL_HAEN |
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PRTCSS_RTC_CCTRL_MAEN |
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PRTCSS_RTC_CCTRL_ALMFLG |
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PRTCSS_RTC_CCTRL_AIEN;
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else
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rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return 0;
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}
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static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u16 days = 0;
|
||||
u8 day0, day1;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&davinci_rtc_lock, flags);
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
|
||||
|
||||
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
|
||||
days |= day1;
|
||||
days <<= 8;
|
||||
days |= day0;
|
||||
|
||||
if (convertfromdays(days, &alm->time) < 0)
|
||||
return -EINVAL;
|
||||
|
||||
alm->pending = !!(rtcss_read(davinci_rtc,
|
||||
PRTCSS_RTC_CCTRL) &
|
||||
PRTCSS_RTC_CCTRL_AIEN);
|
||||
alm->enabled = alm->pending && device_may_wakeup(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
|
||||
{
|
||||
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
u16 days;
|
||||
|
||||
if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
|
||||
&& alm->time.tm_year < 0) {
|
||||
struct rtc_time tm;
|
||||
unsigned long now, then;
|
||||
|
||||
davinci_rtc_read_time(dev, &tm);
|
||||
rtc_tm_to_time(&tm, &now);
|
||||
|
||||
alm->time.tm_mday = tm.tm_mday;
|
||||
alm->time.tm_mon = tm.tm_mon;
|
||||
alm->time.tm_year = tm.tm_year;
|
||||
rtc_tm_to_time(&alm->time, &then);
|
||||
|
||||
if (then < now) {
|
||||
rtc_time_to_tm(now + 24 * 60 * 60, &tm);
|
||||
alm->time.tm_mday = tm.tm_mday;
|
||||
alm->time.tm_mon = tm.tm_mon;
|
||||
alm->time.tm_year = tm.tm_year;
|
||||
}
|
||||
}
|
||||
|
||||
if (convert2days(&days, &alm->time) < 0)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&davinci_rtc_lock, flags);
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
|
||||
|
||||
davinci_rtcss_calendar_wait(davinci_rtc);
|
||||
rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
|
||||
|
||||
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
|
||||
{
|
||||
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
u8 rtc_ctrl;
|
||||
|
||||
spin_lock_irqsave(&davinci_rtc_lock, flags);
|
||||
|
||||
rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
|
||||
|
||||
if (enabled) {
|
||||
while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
|
||||
& PRTCSS_RTC_CTRL_WDTBUS)
|
||||
cpu_relax();
|
||||
|
||||
rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
|
||||
rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
|
||||
|
||||
rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
|
||||
|
||||
rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
|
||||
PRTCSS_RTC_CTRL_TMMD |
|
||||
PRTCSS_RTC_CTRL_TMRFLG;
|
||||
} else
|
||||
rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
|
||||
|
||||
rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
|
||||
|
||||
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
|
||||
{
|
||||
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
|
||||
|
||||
spin_lock_irqsave(&davinci_rtc_lock, flags);
|
||||
|
||||
rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
|
||||
rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
|
||||
|
||||
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct rtc_class_ops davinci_rtc_ops = {
|
||||
.ioctl = davinci_rtc_ioctl,
|
||||
.read_time = davinci_rtc_read_time,
|
||||
.set_time = davinci_rtc_set_time,
|
||||
.alarm_irq_enable = davinci_rtc_alarm_irq_enable,
|
||||
.read_alarm = davinci_rtc_read_alarm,
|
||||
.set_alarm = davinci_rtc_set_alarm,
|
||||
.irq_set_state = davinci_rtc_irq_set_state,
|
||||
.irq_set_freq = davinci_rtc_irq_set_freq,
|
||||
};
|
||||
|
||||
static int __init davinci_rtc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct davinci_rtc *davinci_rtc;
|
||||
struct resource *res, *mem;
|
||||
int ret = 0;
|
||||
|
||||
davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
|
||||
if (!davinci_rtc) {
|
||||
dev_dbg(dev, "could not allocate memory for private data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
davinci_rtc->irq = platform_get_irq(pdev, 0);
|
||||
if (davinci_rtc->irq < 0) {
|
||||
dev_err(dev, "no RTC irq\n");
|
||||
ret = davinci_rtc->irq;
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "no mem resource\n");
|
||||
ret = -EINVAL;
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
davinci_rtc->pbase = res->start;
|
||||
davinci_rtc->base_size = resource_size(res);
|
||||
|
||||
mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
|
||||
pdev->name);
|
||||
if (!mem) {
|
||||
dev_err(dev, "RTC registers at %08x are not free\n",
|
||||
davinci_rtc->pbase);
|
||||
ret = -EBUSY;
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
|
||||
if (!davinci_rtc->base) {
|
||||
dev_err(dev, "unable to ioremap MEM resource\n");
|
||||
ret = -ENOMEM;
|
||||
goto fail2;
|
||||
}
|
||||
|
||||
davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
|
||||
&davinci_rtc_ops, THIS_MODULE);
|
||||
if (IS_ERR(davinci_rtc->rtc)) {
|
||||
dev_err(dev, "unable to register RTC device, err %ld\n",
|
||||
PTR_ERR(davinci_rtc->rtc));
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
|
||||
rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
|
||||
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
|
||||
|
||||
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
|
||||
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
|
||||
|
||||
ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
|
||||
IRQF_DISABLED, "davinci_rtc", davinci_rtc);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "unable to register davinci RTC interrupt\n");
|
||||
goto fail4;
|
||||
}
|
||||
|
||||
/* Enable interrupts */
|
||||
rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
|
||||
rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
|
||||
PRTCSS_RTC_INTC_EXTENA1);
|
||||
|
||||
rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
|
||||
|
||||
platform_set_drvdata(pdev, davinci_rtc);
|
||||
|
||||
device_init_wakeup(&pdev->dev, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
fail4:
|
||||
rtc_device_unregister(davinci_rtc->rtc);
|
||||
fail3:
|
||||
iounmap(davinci_rtc->base);
|
||||
fail2:
|
||||
release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
|
||||
fail1:
|
||||
kfree(davinci_rtc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit davinci_rtc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
|
||||
|
||||
device_init_wakeup(&pdev->dev, 0);
|
||||
|
||||
rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
|
||||
|
||||
free_irq(davinci_rtc->irq, davinci_rtc);
|
||||
|
||||
rtc_device_unregister(davinci_rtc->rtc);
|
||||
|
||||
iounmap(davinci_rtc->base);
|
||||
release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
kfree(davinci_rtc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver davinci_rtc_driver = {
|
||||
.probe = davinci_rtc_probe,
|
||||
.remove = __devexit_p(davinci_rtc_remove),
|
||||
.driver = {
|
||||
.name = "rtc_davinci",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rtc_init(void)
|
||||
{
|
||||
return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
|
||||
}
|
||||
module_init(rtc_init);
|
||||
|
||||
static void __exit rtc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&davinci_rtc_driver);
|
||||
}
|
||||
module_exit(rtc_exit);
|
||||
|
||||
MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
|
||||
MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
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