watchdog: imx93: add watchdog timer on imx93
The WDOG clocks are sourced from lpo_clk, and lpo_clk is the fixed 32KHz. TOVAL contains the 16-bit value used to set the timeout period of the watchdog. When the timeout period exceeds 2 seconds, the value written to the TOVAL register is larger than 16-bit can represent. Enabling watchdog prescaler can solve this problem. Two points need to be aware of: 1. watchdog prescaler enables a fixed 256 pre-scaling of watchdog counter reference clock 2. reconfiguration takes about 55ms on imx93 Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220825083256.14565-8-alice.guo@oss.nxp.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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8ed2dc4855
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@ -9,6 +9,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/watchdog.h>
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@ -52,11 +53,17 @@ module_param(nowayout, bool, 0000);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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struct imx_wdt_hw_feature {
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bool prescaler_enable;
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u32 wdog_clock_rate;
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};
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struct imx7ulp_wdt_device {
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struct watchdog_device wdd;
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void __iomem *base;
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struct clk *clk;
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bool post_rcs_wait;
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const struct imx_wdt_hw_feature *hw;
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};
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static int imx7ulp_wdt_wait_ulk(void __iomem *base)
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@ -179,7 +186,7 @@ static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
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unsigned int timeout)
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{
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
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u32 toval = WDOG_CLOCK_RATE * timeout;
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u32 toval = wdt->hw->wdog_clock_rate * timeout;
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u32 val;
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int ret;
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u32 loop = RETRY_MAX;
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@ -276,6 +283,9 @@ static int imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout
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int ret;
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u32 loop = RETRY_MAX;
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if (wdt->hw->prescaler_enable)
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val |= WDOG_CS_PRES;
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do {
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ret = _imx7ulp_wdt_init(wdt, timeout, val);
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toval = readl(wdt->base + WDOG_TOVAL);
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@ -346,7 +356,9 @@ static int imx7ulp_wdt_probe(struct platform_device *pdev)
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watchdog_stop_on_reboot(wdog);
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watchdog_stop_on_unregister(wdog);
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watchdog_set_drvdata(wdog, imx7ulp_wdt);
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ret = imx7ulp_wdt_init(imx7ulp_wdt, wdog->timeout * WDOG_CLOCK_RATE);
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imx7ulp_wdt->hw = of_device_get_match_data(dev);
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ret = imx7ulp_wdt_init(imx7ulp_wdt, wdog->timeout * imx7ulp_wdt->hw->wdog_clock_rate);
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if (ret)
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return ret;
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@ -368,7 +380,7 @@ static int __maybe_unused imx7ulp_wdt_suspend_noirq(struct device *dev)
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static int __maybe_unused imx7ulp_wdt_resume_noirq(struct device *dev)
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{
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struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
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u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE;
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u32 timeout = imx7ulp_wdt->wdd.timeout * imx7ulp_wdt->hw->wdog_clock_rate;
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int ret;
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ret = clk_prepare_enable(imx7ulp_wdt->clk);
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@ -389,9 +401,20 @@ static const struct dev_pm_ops imx7ulp_wdt_pm_ops = {
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imx7ulp_wdt_resume_noirq)
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};
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static const struct imx_wdt_hw_feature imx7ulp_wdt_hw = {
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.prescaler_enable = false,
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.wdog_clock_rate = 1000,
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};
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static const struct imx_wdt_hw_feature imx93_wdt_hw = {
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.prescaler_enable = true,
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.wdog_clock_rate = 125,
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};
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static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
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{ .compatible = "fsl,imx8ulp-wdt", },
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{ .compatible = "fsl,imx7ulp-wdt", },
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{ .compatible = "fsl,imx8ulp-wdt", .data = &imx7ulp_wdt_hw, },
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{ .compatible = "fsl,imx7ulp-wdt", .data = &imx7ulp_wdt_hw, },
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{ .compatible = "fsl,imx93-wdt", .data = &imx93_wdt_hw, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
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