drm/tegra: Fixes for v3.20-rc1
This fixes a bit of fallout that was caused by the atomic modesetting driver conversion and some last-minute changes in the DRM atomic core. It also fixes a bug exposed by recent changes in the clock framework which results in non-working HDMI. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJU5eTAAAoJEN0jrNd/PrOhyx0P/0oLSRfqddmgqtWYLG5Xprc5 xwI6N3Elil9dMdl+QnVkh0Bd2dN3QiSobpJlLLu0C4eQwSKNGPKrMITdoz2kxdLm V2hswNN9iVf/g8ZvR/VoLBYaWSZER9OVgSKx6kqih4X1hJNyGpBlux3MPxWQ2MTC s3fIq8gdSgxcNwno4R1nfx0SOPxVRPW72qfPsY2hZQFE/6jcZ5k6V6BPqcu69mKz af8SKrEIXN57Lxq54+qlzVrFxKCzQmj9lLeX3yty9Hj+SBqm0ybQNbnCrJE2Kcsi xkYhA0JxUerw30sb5HJkvJqmWltxoaf0ZDaQOPd01ZTxIOGpsObN2o3h0lBaVt6G lSXXKdLF9AFtYHzVJq6L7KkpsOK40fM0tks+K/4lhPRIZmwG7A46hRZbVnJfiCUv PEYdwzXvNrz6jEACw4Cu986556n3FCeR6Qb/4T3gyCNh9VbICxcOTaDwTalGhw44 eLFEvY1KqmAbQtrf6soRlVcMySZ5QEJAZtRxNsYcjhHCSQOmcx6YIRiOJ2aA+BFe WjHily2N4g7afetc8TWDkFvf8niLVBiyXisEtX90Ef13LRbHVXAY2b4oKiJN6ljX kSb1uAG1BbLChETluAAj4CN6QQigzbMYjkW5Zrv9xN/Aj9w52YQK2bW9ydNH3ULW UofsqSV4zUdXxcY2NSCQ =PQiO -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-fixes drm/tegra: Fixes for v3.20-rc1 This fixes a bit of fallout that was caused by the atomic modesetting driver conversion and some last-minute changes in the DRM atomic core. It also fixes a bug exposed by recent changes in the clock framework which results in non-working HDMI. * tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: dc: Move more code into ->init() drm/tegra: dc: Wire up CRTC parent of atomic state drm/tegra: dc: Reset state's active_changed field drm/tegra: hdmi: Explicitly set clock rate
This commit is contained in:
Dave Airlie
Коммит
8ee351625e
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@ -997,8 +997,10 @@ static void tegra_crtc_reset(struct drm_crtc *crtc)
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crtc->state = NULL;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state)
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if (state) {
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crtc->state = &state->base;
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crtc->state->crtc = crtc;
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}
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}
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static struct drm_crtc_state *
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@ -1012,6 +1014,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
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return NULL;
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copy->base.mode_changed = false;
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copy->base.active_changed = false;
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copy->base.planes_changed = false;
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copy->base.event = NULL;
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@ -1227,9 +1230,6 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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/* program display mode */
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tegra_dc_set_timings(dc, mode);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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/* interlacing isn't supported yet, so disable it */
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if (dc->soc->supports_interlacing) {
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value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
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@ -1252,42 +1252,7 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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static void tegra_crtc_prepare(struct drm_crtc *crtc)
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{
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struct tegra_dc *dc = to_tegra_dc(crtc);
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unsigned int syncpt;
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unsigned long value;
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drm_crtc_vblank_off(crtc);
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if (dc->pipe)
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syncpt = SYNCPT_VBLANK1;
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else
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syncpt = SYNCPT_VBLANK0;
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/* initialize display controller */
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tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
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tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
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/* initialize timer */
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
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WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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}
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static void tegra_crtc_commit(struct drm_crtc *crtc)
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@ -1664,6 +1629,8 @@ static int tegra_dc_init(struct host1x_client *client)
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struct tegra_drm *tegra = drm->dev_private;
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struct drm_plane *primary = NULL;
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struct drm_plane *cursor = NULL;
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unsigned int syncpt;
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u32 value;
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int err;
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if (tegra->domain) {
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@ -1730,6 +1697,40 @@ static int tegra_dc_init(struct host1x_client *client)
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goto cleanup;
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}
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/* initialize display controller */
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if (dc->pipe)
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syncpt = SYNCPT_VBLANK1;
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else
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syncpt = SYNCPT_VBLANK0;
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tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
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tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
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/* initialize timer */
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
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WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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return 0;
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cleanup:
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@ -851,6 +851,14 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
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h_back_porch = mode->htotal - mode->hsync_end;
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h_front_porch = mode->hsync_start - mode->hdisplay;
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err = clk_set_rate(hdmi->clk, pclk);
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if (err < 0) {
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dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
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err);
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}
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DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
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/* power up sequence */
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value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
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value &= ~SOR_PLL_PDBG;
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