tg3: Move napi to per-int struct
This patch creates a per-interrupt data structure, moves the napi member over, and creates a tg3 pointer back to the device structure. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
07b0173cb5
Коммит
8ef0442f98
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@ -687,7 +687,7 @@ static void tg3_restart_ints(struct tg3 *tp)
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static inline void tg3_netif_stop(struct tg3 *tp)
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{
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tp->dev->trans_start = jiffies; /* prevent tx timeout */
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napi_disable(&tp->napi);
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napi_disable(&tp->napi[0].napi);
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netif_tx_disable(tp->dev);
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}
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@ -698,7 +698,7 @@ static inline void tg3_netif_start(struct tg3 *tp)
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* so long as all callers are assured to have free tx slots
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* (such as after tg3_init_hw)
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*/
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napi_enable(&tp->napi);
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napi_enable(&tp->napi[0].napi);
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tp->hw_status->status |= SD_STATUS_UPDATED;
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tg3_enable_ints(tp);
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}
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@ -4447,13 +4447,6 @@ static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
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src_map->skb = NULL;
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}
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#if TG3_VLAN_TAG_USED
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static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
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{
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return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
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}
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#endif
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/* The RX ring scheme is composed of multiple rings which post fresh
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* buffers to the chip, and one special ring the chip uses to report
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* status back to the host.
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@ -4591,11 +4584,11 @@ static int tg3_rx(struct tg3 *tp, int budget)
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#if TG3_VLAN_TAG_USED
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if (tp->vlgrp != NULL &&
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desc->type_flags & RXD_FLAG_VLAN) {
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tg3_vlan_rx(tp, skb,
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desc->err_vlan & RXD_VLAN_MASK);
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vlan_gro_receive(&tp->napi[0].napi, tp->vlgrp,
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desc->err_vlan & RXD_VLAN_MASK, skb);
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} else
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#endif
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napi_gro_receive(&tp->napi, skb);
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napi_gro_receive(&tp->napi[0].napi, skb);
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received++;
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budget--;
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@ -4686,7 +4679,8 @@ static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
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static int tg3_poll(struct napi_struct *napi, int budget)
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{
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struct tg3 *tp = container_of(napi, struct tg3, napi);
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struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
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struct tg3 *tp = tnapi->tp;
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int work_done = 0;
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struct tg3_hw_status *sblk = tp->hw_status;
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@ -4770,7 +4764,7 @@ static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
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prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
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if (likely(!tg3_irq_sync(tp)))
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napi_schedule(&tp->napi);
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napi_schedule(&tp->napi[0].napi);
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return IRQ_HANDLED;
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}
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@ -4795,7 +4789,7 @@ static irqreturn_t tg3_msi(int irq, void *dev_id)
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*/
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
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if (likely(!tg3_irq_sync(tp)))
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napi_schedule(&tp->napi);
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napi_schedule(&tp->napi[0].napi);
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return IRQ_RETVAL(1);
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}
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@ -4837,7 +4831,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id)
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sblk->status &= ~SD_STATUS_UPDATED;
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if (likely(tg3_has_work(tp))) {
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prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
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napi_schedule(&tp->napi);
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napi_schedule(&tp->napi[0].napi);
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} else {
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/* No work, shared interrupt perhaps? re-enable
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* interrupts, and flush that PCI write
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@ -4895,7 +4889,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
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prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
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napi_schedule(&tp->napi);
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napi_schedule(&tp->napi[0].napi);
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out:
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return IRQ_RETVAL(handled);
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@ -4936,7 +4930,7 @@ static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
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tg3_full_unlock(tp);
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del_timer_sync(&tp->timer);
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tp->irq_sync = 0;
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napi_enable(&tp->napi);
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napi_enable(&tp->napi[0].napi);
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dev_close(tp->dev);
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tg3_full_lock(tp, 0);
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}
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@ -7935,7 +7929,7 @@ static int tg3_open(struct net_device *dev)
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tg3_ints_init(tp);
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napi_enable(&tp->napi);
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napi_enable(&tp->napi[0].napi);
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err = tg3_request_irq(tp);
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@ -8011,7 +8005,7 @@ err_out2:
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free_irq(tp->pdev->irq, dev);
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err_out1:
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napi_disable(&tp->napi);
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napi_disable(&tp->napi[0].napi);
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tg3_ints_fini(tp);
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tg3_free_consistent(tp);
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return err;
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@ -8252,7 +8246,7 @@ static int tg3_close(struct net_device *dev)
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{
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struct tg3 *tp = netdev_priv(dev);
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napi_disable(&tp->napi);
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napi_disable(&tp->napi[0].napi);
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cancel_work_sync(&tp->reset_task);
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netif_stop_queue(dev);
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@ -13396,7 +13390,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
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tp->tx_pending = TG3_DEF_TX_RING_PENDING;
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netif_napi_add(dev, &tp->napi, tg3_poll, 64);
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tp->napi[0].tp = tp;
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netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
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dev->ethtool_ops = &tg3_ethtool_ops;
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dev->watchdog_timeo = TG3_TX_TIMEOUT;
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dev->irq = pdev->irq;
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@ -2487,6 +2487,13 @@ struct tg3_rx_prodring_set {
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dma_addr_t rx_jmb_mapping;
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};
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#define TG3_IRQ_MAX_VECS 1
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struct tg3_napi {
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struct napi_struct napi ____cacheline_aligned;
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struct tg3 *tp;
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};
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struct tg3 {
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/* begin "general, frequently-used members" cacheline section */
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@ -2558,7 +2565,7 @@ struct tg3 {
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dma_addr_t tx_desc_mapping;
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/* begin "rx thread" cacheline section */
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struct napi_struct napi;
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struct tg3_napi napi[TG3_IRQ_MAX_VECS];
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void (*write32_rx_mbox) (struct tg3 *, u32,
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u32);
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u32 rx_rcb_ptr;
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