SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: spi-devel-general@lists.sourceforge.net Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
Ralf Baechle
Родитель
3f348c5d1a
Коммит
8efaef4dc8
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@ -0,0 +1,23 @@
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/*
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* Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _ATH79_SPI_PLATFORM_H
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#define _ATH79_SPI_PLATFORM_H
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struct ath79_spi_platform_data {
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unsigned bus_num;
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unsigned num_chipselect;
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};
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struct ath79_spi_controller_data {
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unsigned gpio;
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};
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#endif /* _ATH79_SPI_PLATFORM_H */
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@ -53,6 +53,14 @@ if SPI_MASTER
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comment "SPI Master Controller Drivers"
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config SPI_ATH79
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tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
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depends on ATH79 && GENERIC_GPIO
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select SPI_BITBANG
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help
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This enables support for the SPI controller present on the
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Atheros AR71XX/AR724X/AR913X SoCs.
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config SPI_ATMEL
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tristate "Atmel SPI Controller"
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depends on (ARCH_AT91 || AVR32)
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@ -10,6 +10,7 @@ obj-$(CONFIG_SPI_MASTER) += spi.o
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# SPI master controller drivers (bus)
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obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
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obj-$(CONFIG_SPI_ATH79) += ath79_spi.o
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obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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@ -0,0 +1,292 @@
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/*
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* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
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*
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* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This driver has been based on the spi-gpio.c:
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* Copyright (C) 2006,2008 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79_spi_platform.h>
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#define DRV_NAME "ath79-spi"
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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u32 reg_ctrl;
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void __iomem *base;
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};
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
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{
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return ioread32(sp->base + reg);
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}
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static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
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{
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iowrite32(val, sp->base + reg);
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}
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static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
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{
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return spi_master_get_devdata(spi->master);
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}
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static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
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if (is_active) {
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/* set initial clock polarity */
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if (spi->mode & SPI_CPOL)
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sp->ioc_base |= AR71XX_SPI_IOC_CLK;
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else
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sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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if (spi->chip_select) {
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struct ath79_spi_controller_data *cdata = spi->controller_data;
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/* SPI is normally active-low */
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gpio_set_value(cdata->gpio, cs_high);
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} else {
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if (cs_high)
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sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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else
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sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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}
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static int ath79_spi_setup_cs(struct spi_device *spi)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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struct ath79_spi_controller_data *cdata;
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cdata = spi->controller_data;
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if (spi->chip_select && !cdata)
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return -EINVAL;
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/* enable GPIO mode */
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ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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/* save CTRL register */
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sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
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sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
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/* TODO: setup speed? */
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ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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if (spi->chip_select) {
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int status = 0;
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status = gpio_request(cdata->gpio, dev_name(&spi->dev));
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if (status)
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return status;
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status = gpio_direction_output(cdata->gpio,
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spi->mode & SPI_CS_HIGH);
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if (status) {
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gpio_free(cdata->gpio);
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return status;
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}
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} else {
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if (spi->mode & SPI_CS_HIGH)
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sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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else
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sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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return 0;
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}
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static void ath79_spi_cleanup_cs(struct spi_device *spi)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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if (spi->chip_select) {
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struct ath79_spi_controller_data *cdata = spi->controller_data;
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gpio_free(cdata->gpio);
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}
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/* restore CTRL register */
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ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
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/* disable GPIO mode */
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ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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}
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static int ath79_spi_setup(struct spi_device *spi)
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{
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int status = 0;
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if (spi->bits_per_word > 32)
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return -EINVAL;
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if (!spi->controller_state) {
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status = ath79_spi_setup_cs(spi);
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if (status)
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return status;
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}
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status = spi_bitbang_setup(spi);
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if (status && !spi->controller_state)
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ath79_spi_cleanup_cs(spi);
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return status;
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}
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static void ath79_spi_cleanup(struct spi_device *spi)
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{
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ath79_spi_cleanup_cs(spi);
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spi_bitbang_cleanup(spi);
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}
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static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
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u32 word, u8 bits)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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u32 ioc = sp->ioc_base;
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/* clock starts at inactive polarity */
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for (word <<= (32 - bits); likely(bits); bits--) {
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u32 out;
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if (word & (1 << 31))
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out = ioc | AR71XX_SPI_IOC_DO;
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else
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out = ioc & ~AR71XX_SPI_IOC_DO;
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/* setup MSB (to slave) on trailing edge */
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
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word <<= 1;
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}
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return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
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}
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static __devinit int ath79_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct ath79_spi *sp;
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struct ath79_spi_platform_data *pdata;
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struct resource *r;
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int ret;
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master = spi_alloc_master(&pdev->dev, sizeof(*sp));
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if (master == NULL) {
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dev_err(&pdev->dev, "failed to allocate spi master\n");
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return -ENOMEM;
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}
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sp = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, sp);
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pdata = pdev->dev.platform_data;
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master->setup = ath79_spi_setup;
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master->cleanup = ath79_spi_cleanup;
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if (pdata) {
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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} else {
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master->bus_num = -1;
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master->num_chipselect = 1;
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}
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sp->bitbang.master = spi_master_get(master);
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sp->bitbang.chipselect = ath79_spi_chipselect;
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sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
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sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
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sp->bitbang.flags = SPI_CS_HIGH;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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ret = -ENOENT;
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goto err_put_master;
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}
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sp->base = ioremap(r->start, r->end - r->start + 1);
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if (!sp->base) {
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ret = -ENXIO;
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goto err_put_master;
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}
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ret = spi_bitbang_start(&sp->bitbang);
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if (ret)
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goto err_unmap;
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return 0;
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err_unmap:
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iounmap(sp->base);
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err_put_master:
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platform_set_drvdata(pdev, NULL);
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spi_master_put(sp->bitbang.master);
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return ret;
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}
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static __devexit int ath79_spi_remove(struct platform_device *pdev)
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{
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struct ath79_spi *sp = platform_get_drvdata(pdev);
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spi_bitbang_stop(&sp->bitbang);
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iounmap(sp->base);
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platform_set_drvdata(pdev, NULL);
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spi_master_put(sp->bitbang.master);
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return 0;
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}
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static struct platform_driver ath79_spi_driver = {
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.probe = ath79_spi_probe,
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.remove = __devexit_p(ath79_spi_remove),
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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};
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static __init int ath79_spi_init(void)
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{
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return platform_driver_register(&ath79_spi_driver);
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}
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module_init(ath79_spi_init);
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static __exit void ath79_spi_exit(void)
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{
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platform_driver_unregister(&ath79_spi_driver);
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}
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module_exit(ath79_spi_exit);
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MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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