uwb: add the driver to enumerate WHCI capabilities
This enumerates the capabilties of a WHCI device, adding a umc device for each one. Signed-off-by: David Vrabel <david.vrabel@csr.com>
This commit is contained in:
David Vrabel
David Vrabel
Родитель
da389eac31
Коммит
8f1b678ab9
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@ -1,5 +1,5 @@
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obj-$(CONFIG_UWB) += uwb.o
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obj-$(CONFIG_UWB_WHCI) += umc.o
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obj-$(CONFIG_UWB_WHCI) += umc.o whci.o
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uwb-objs := \
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address.o \
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@ -0,0 +1,269 @@
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/*
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* WHCI UWB Multi-interface Controller enumerator.
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*
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* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
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*
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* This file is released under the GNU GPL v2.
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/uwb/whci.h>
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#include <linux/uwb/umc.h>
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struct whci_card {
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struct pci_dev *pci;
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void __iomem *uwbbase;
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u8 n_caps;
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struct umc_dev *devs[0];
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};
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/* Fix faulty HW :( */
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static
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u64 whci_capdata_quirks(struct whci_card *card, u64 capdata)
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{
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u64 capdata_orig = capdata;
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struct pci_dev *pci_dev = card->pci;
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if (pci_dev->vendor == PCI_VENDOR_ID_INTEL
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&& (pci_dev->device == 0x0c3b || pci_dev->device == 0004)
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&& pci_dev->class == 0x0d1010) {
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switch (UWBCAPDATA_TO_CAP_ID(capdata)) {
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/* WLP capability has 0x100 bytes of aperture */
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case 0x80:
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capdata |= 0x40 << 8; break;
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/* WUSB capability has 0x80 bytes of aperture
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* and ID is 1 */
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case 0x02:
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capdata &= ~0xffff;
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capdata |= 0x2001;
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break;
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}
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}
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if (capdata_orig != capdata)
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dev_warn(&pci_dev->dev,
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"PCI v%04x d%04x c%06x#%02x: "
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"corrected capdata from %016Lx to %016Lx\n",
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pci_dev->vendor, pci_dev->device, pci_dev->class,
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(unsigned)UWBCAPDATA_TO_CAP_ID(capdata),
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(unsigned long long)capdata_orig,
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(unsigned long long)capdata);
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return capdata;
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}
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/**
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* whci_wait_for - wait for a WHCI register to be set
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*
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* Polls (for at most @max_ms ms) until '*@reg & @mask == @result'.
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*/
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int whci_wait_for(struct device *dev, u32 __iomem *reg, u32 mask, u32 result,
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unsigned long max_ms, const char *tag)
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{
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unsigned t = 0;
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u32 val;
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for (;;) {
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val = le_readl(reg);
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if ((val & mask) == result)
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break;
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msleep(10);
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if (t >= max_ms) {
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dev_err(dev, "timed out waiting for %s ", tag);
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return -ETIMEDOUT;
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}
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t += 10;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(whci_wait_for);
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/*
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* NOTE: the capinfo and capdata registers are slightly different
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* (size and cap-id fields). So for cap #0, we need to fill
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* in. Size comes from the size of the register block
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* (statically calculated); cap_id comes from nowhere, we use
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* zero, that is reserved, for the radio controller, because
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* none was defined at the spec level.
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*/
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static int whci_add_cap(struct whci_card *card, int n)
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{
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struct umc_dev *umc;
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u64 capdata;
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int bar, err;
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umc = umc_device_create(&card->pci->dev, n);
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if (umc == NULL)
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return -ENOMEM;
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capdata = le_readq(card->uwbbase + UWBCAPDATA(n));
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bar = UWBCAPDATA_TO_BAR(capdata) << 1;
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capdata = whci_capdata_quirks(card, capdata);
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/* Capability 0 is the radio controller. It's size is 32
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* bytes (WHCI0.95[2.3, T2-9]). */
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umc->version = UWBCAPDATA_TO_VERSION(capdata);
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umc->cap_id = n == 0 ? 0 : UWBCAPDATA_TO_CAP_ID(capdata);
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umc->bar = bar;
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umc->resource.start = pci_resource_start(card->pci, bar)
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+ UWBCAPDATA_TO_OFFSET(capdata);
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umc->resource.end = umc->resource.start
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+ (n == 0 ? 0x20 : UWBCAPDATA_TO_SIZE(capdata)) - 1;
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umc->resource.name = umc->dev.bus_id;
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umc->resource.flags = card->pci->resource[bar].flags;
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umc->resource.parent = &card->pci->resource[bar];
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umc->irq = card->pci->irq;
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err = umc_device_register(umc);
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if (err < 0)
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goto error;
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card->devs[n] = umc;
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return 0;
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error:
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kfree(umc);
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return err;
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}
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static void whci_del_cap(struct whci_card *card, int n)
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{
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struct umc_dev *umc = card->devs[n];
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if (umc != NULL)
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umc_device_unregister(umc);
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}
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static int whci_n_caps(struct pci_dev *pci)
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{
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void __iomem *uwbbase;
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u64 capinfo;
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uwbbase = pci_iomap(pci, 0, 8);
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if (!uwbbase)
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return -ENOMEM;
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capinfo = le_readq(uwbbase + UWBCAPINFO);
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pci_iounmap(pci, uwbbase);
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return UWBCAPINFO_TO_N_CAPS(capinfo);
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}
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static int whci_probe(struct pci_dev *pci, const struct pci_device_id *id)
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{
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struct whci_card *card;
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int err, n_caps, n;
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err = pci_enable_device(pci);
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if (err < 0)
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goto error;
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pci_enable_msi(pci);
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pci_set_master(pci);
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err = -ENXIO;
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if (!pci_set_dma_mask(pci, DMA_64BIT_MASK))
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pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
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else if (!pci_set_dma_mask(pci, DMA_32BIT_MASK))
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pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
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else
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goto error_dma;
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err = n_caps = whci_n_caps(pci);
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if (n_caps < 0)
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goto error_ncaps;
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err = -ENOMEM;
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card = kzalloc(sizeof(struct whci_card)
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+ sizeof(struct whci_dev *) * (n_caps + 1),
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GFP_KERNEL);
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if (card == NULL)
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goto error_kzalloc;
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card->pci = pci;
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card->n_caps = n_caps;
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err = -EBUSY;
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if (!request_mem_region(pci_resource_start(pci, 0),
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UWBCAPDATA_SIZE(card->n_caps),
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"whci (capability data)"))
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goto error_request_memregion;
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err = -ENOMEM;
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card->uwbbase = pci_iomap(pci, 0, UWBCAPDATA_SIZE(card->n_caps));
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if (!card->uwbbase)
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goto error_iomap;
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/* Add each capability. */
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for (n = 0; n <= card->n_caps; n++) {
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err = whci_add_cap(card, n);
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if (err < 0 && n == 0) {
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dev_err(&pci->dev, "cannot bind UWB radio controller:"
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" %d\n", err);
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goto error_bind;
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}
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if (err < 0)
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dev_warn(&pci->dev, "warning: cannot bind capability "
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"#%u: %d\n", n, err);
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}
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pci_set_drvdata(pci, card);
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return 0;
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error_bind:
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pci_iounmap(pci, card->uwbbase);
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error_iomap:
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release_mem_region(pci_resource_start(pci, 0), UWBCAPDATA_SIZE(card->n_caps));
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error_request_memregion:
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kfree(card);
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error_kzalloc:
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error_ncaps:
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error_dma:
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pci_disable_msi(pci);
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pci_disable_device(pci);
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error:
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return err;
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}
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static void whci_remove(struct pci_dev *pci)
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{
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struct whci_card *card = pci_get_drvdata(pci);
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int n;
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pci_set_drvdata(pci, NULL);
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/* Unregister each capability in reverse (so the master device
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* is unregistered last). */
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for (n = card->n_caps; n >= 0 ; n--)
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whci_del_cap(card, n);
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pci_iounmap(pci, card->uwbbase);
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release_mem_region(pci_resource_start(pci, 0), UWBCAPDATA_SIZE(card->n_caps));
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kfree(card);
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pci_disable_msi(pci);
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pci_disable_device(pci);
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}
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static struct pci_device_id whci_id_table[] = {
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{ PCI_DEVICE_CLASS(PCI_CLASS_WIRELESS_WHCI, ~0) },
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{ 0 },
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};
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MODULE_DEVICE_TABLE(pci, whci_id_table);
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static struct pci_driver whci_driver = {
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.name = "whci",
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.id_table = whci_id_table,
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.probe = whci_probe,
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.remove = whci_remove,
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};
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static int __init whci_init(void)
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{
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return pci_register_driver(&whci_driver);
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}
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static void __exit whci_exit(void)
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{
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pci_unregister_driver(&whci_driver);
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}
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module_init(whci_init);
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module_exit(whci_exit);
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MODULE_DESCRIPTION("WHCI UWB Multi-interface Controller enumerator");
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MODULE_AUTHOR("Cambridge Silicon Radio Ltd.");
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MODULE_LICENSE("GPL");
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@ -0,0 +1,117 @@
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/*
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* Wireless Host Controller Interface for Ultra-Wide-Band and Wireless USB
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*
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* Copyright (C) 2005-2006 Intel Corporation
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* Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*
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*
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* References:
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* [WHCI] Wireless Host Controller Interface Specification for
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* Certified Wireless Universal Serial Bus, revision 0.95.
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*/
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#ifndef _LINUX_UWB_WHCI_H_
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#define _LINUX_UWB_WHCI_H_
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#include <linux/pci.h>
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/*
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* UWB interface capability registers (offsets from UWBBASE)
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*
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* [WHCI] section 2.2
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*/
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#define UWBCAPINFO 0x00 /* == UWBCAPDATA(0) */
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# define UWBCAPINFO_TO_N_CAPS(c) (((c) >> 0) & 0xFull)
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#define UWBCAPDATA(n) (8*(n))
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# define UWBCAPDATA_TO_VERSION(c) (((c) >> 32) & 0xFFFFull)
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# define UWBCAPDATA_TO_OFFSET(c) (((c) >> 18) & 0x3FFFull)
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# define UWBCAPDATA_TO_BAR(c) (((c) >> 16) & 0x3ull)
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# define UWBCAPDATA_TO_SIZE(c) ((((c) >> 8) & 0xFFull) * sizeof(u32))
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# define UWBCAPDATA_TO_CAP_ID(c) (((c) >> 0) & 0xFFull)
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/* Size of the WHCI capability data (including the RC capability) for
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a device with n capabilities. */
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#define UWBCAPDATA_SIZE(n) (8 + 8*(n))
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/*
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* URC registers (offsets from URCBASE)
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*
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* [WHCI] section 2.3
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*/
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#define URCCMD 0x00
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# define URCCMD_RESET (1 << 31) /* UMC Hardware reset */
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# define URCCMD_RS (1 << 30) /* Run/Stop */
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# define URCCMD_EARV (1 << 29) /* Event Address Register Valid */
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# define URCCMD_ACTIVE (1 << 15) /* Command is active */
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# define URCCMD_IWR (1 << 14) /* Interrupt When Ready */
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# define URCCMD_SIZE_MASK 0x00000fff /* Command size mask */
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#define URCSTS 0x04
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# define URCSTS_EPS (1 << 17) /* Event Processing Status */
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# define URCSTS_HALTED (1 << 16) /* RC halted */
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# define URCSTS_HSE (1 << 10) /* Host System Error...fried */
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# define URCSTS_ER (1 << 9) /* Event Ready */
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# define URCSTS_RCI (1 << 8) /* Ready for Command Interrupt */
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# define URCSTS_INT_MASK 0x00000700 /* URC interrupt sources */
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# define URCSTS_ISI 0x000000ff /* Interrupt Source Identification */
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#define URCINTR 0x08
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# define URCINTR_EN_ALL 0x000007ff /* Enable all interrupt sources */
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#define URCCMDADDR 0x10
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#define URCEVTADDR 0x18
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# define URCEVTADDR_OFFSET_MASK 0xfff /* Event pointer offset mask */
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/** Write 32 bit @value to little endian register at @addr */
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static inline
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void le_writel(u32 value, void __iomem *addr)
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{
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iowrite32(value, addr);
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}
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/** Read from 32 bit little endian register at @addr */
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static inline
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u32 le_readl(void __iomem *addr)
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{
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return ioread32(addr);
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}
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/** Write 64 bit @value to little endian register at @addr */
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static inline
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void le_writeq(u64 value, void __iomem *addr)
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{
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iowrite32(value, addr);
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iowrite32(value >> 32, addr + 4);
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}
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/** Read from 64 bit little endian register at @addr */
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static inline
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u64 le_readq(void __iomem *addr)
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{
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u64 value;
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value = ioread32(addr);
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value |= (u64)ioread32(addr + 4) << 32;
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return value;
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}
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extern int whci_wait_for(struct device *dev, u32 __iomem *reg,
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u32 mask, u32 result,
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unsigned long max_ms, const char *tag);
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#endif /* #ifndef _LINUX_UWB_WHCI_H_ */
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