ARM: EXYNOS4: Add usb host phy control
EXYNOS4 has 2 phys for usb host and usb device. This patch supports to control usb host phy of EXYNOS4. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Joonyoung Shim
Greg Kroah-Hartman
Родитель
3e11266212
Коммит
8f1d169f99
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@ -54,3 +54,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
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obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
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obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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obj-$(CONFIG_USB_SUPPORT) += usb-phy.o
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@ -97,7 +97,12 @@ static struct map_desc exynos4_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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}, {
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.virtual = (unsigned long)S5P_VA_USB_HSPHY,
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.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}
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};
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static void exynos4_idle(void)
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@ -102,6 +102,7 @@
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS4_PA_EHCI 0x12580000
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#define EXYNOS4_PA_HSPHY 0x125B0000
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#define EXYNOS4_PA_UART 0x13800000
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@ -33,6 +33,9 @@
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#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
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#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
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#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
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#define S5P_USBHOST_PHY_ENABLE (1 << 0)
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#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
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#define S5P_MIPI_DPHY_ENABLE (1 << 0)
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#define S5P_MIPI_DPHY_SRESETN (1 << 1)
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@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Author: Joonyoung Shim <jy0922.shim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __PLAT_S5P_REGS_USB_PHY_H
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#define __PLAT_S5P_REGS_USB_PHY_H
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#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S5P_VA_USB_HSPHY)
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#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
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#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
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#define PHY1_HSIC1_SLEEP (1 << 12)
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#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
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#define PHY1_HSIC0_SLEEP (1 << 10)
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#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
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#define PHY1_STD_NORMAL_MASK (0x7 << 6)
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#define PHY1_STD_SLEEP (1 << 8)
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#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
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#define PHY1_STD_FORCE_SUSPEND (1 << 6)
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#define PHY0_NORMAL_MASK (0x39 << 0)
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#define PHY0_SLEEP (1 << 5)
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#define PHY0_OTG_DISABLE (1 << 4)
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#define PHY0_ANALOG_POWERDOWN (1 << 3)
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#define PHY0_FORCE_SUSPEND (1 << 0)
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#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
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#define PHY1_COMMON_ON_N (1 << 7)
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#define PHY0_COMMON_ON_N (1 << 4)
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#define PHY0_ID_PULLUP (1 << 2)
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#define CLKSEL_MASK (0x3 << 0)
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#define CLKSEL_SHIFT (0)
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#define CLKSEL_48M (0x0 << 0)
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#define CLKSEL_12M (0x2 << 0)
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#define CLKSEL_24M (0x3 << 0)
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#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
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#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
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#define HOST_LINK_PORT2_SWRST (1 << 9)
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#define HOST_LINK_PORT1_SWRST (1 << 8)
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#define HOST_LINK_PORT0_SWRST (1 << 7)
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#define HOST_LINK_ALL_SWRST (1 << 6)
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#define PHY1_SWRST_MASK (0x7 << 3)
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#define PHY1_HSIC_SWRST (1 << 5)
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#define PHY1_STD_SWRST (1 << 4)
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#define PHY1_ALL_SWRST (1 << 3)
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#define PHY0_SWRST_MASK (0x7 << 0)
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#define PHY0_PHYLINK_SWRST (1 << 2)
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#define PHY0_HLINK_SWRST (1 << 1)
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#define PHY0_SWRST (1 << 0)
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#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
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#define FPENABLEN (1 << 0)
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#endif /* __PLAT_S5P_REGS_USB_PHY_H */
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@ -0,0 +1,136 @@
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/*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Author: Joonyoung Shim <jy0922.shim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <mach/regs-pmu.h>
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#include <mach/regs-usb-phy.h>
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#include <plat/cpu.h>
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#include <plat/usb-phy.h>
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static int exynos4_usb_phy1_init(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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struct clk *xusbxti_clk;
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u32 phyclk;
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u32 rstcon;
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int err;
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otg_clk = clk_get(&pdev->dev, "otg");
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if (IS_ERR(otg_clk)) {
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dev_err(&pdev->dev, "Failed to get otg clock\n");
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return PTR_ERR(otg_clk);
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}
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err = clk_enable(otg_clk);
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if (err) {
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clk_put(otg_clk);
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return err;
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}
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writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
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S5P_USBHOST_PHY_CONTROL);
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
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xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
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if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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}
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clk_put(xusbxti_clk);
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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/* floating prevention logic: disable */
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writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
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/* set to normal HSIC 0 and 1 of PHY1 */
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writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
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EXYNOS4_PHYPWR);
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/* set to normal standard USB of PHY1 */
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writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
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/* reset all ports of both PHY and Link */
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rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
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PHY1_SWRST_MASK;
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writel(rstcon, EXYNOS4_RSTCON);
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udelay(10);
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rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
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writel(rstcon, EXYNOS4_RSTCON);
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udelay(50);
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clk_disable(otg_clk);
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clk_put(otg_clk);
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return 0;
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}
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static int exynos4_usb_phy1_exit(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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int err;
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otg_clk = clk_get(&pdev->dev, "otg");
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if (IS_ERR(otg_clk)) {
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dev_err(&pdev->dev, "Failed to get otg clock\n");
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return PTR_ERR(otg_clk);
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}
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err = clk_enable(otg_clk);
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if (err) {
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clk_put(otg_clk);
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return err;
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}
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writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
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EXYNOS4_PHYPWR);
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writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
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S5P_USBHOST_PHY_CONTROL);
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clk_disable(otg_clk);
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clk_put(otg_clk);
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return 0;
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}
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int s5p_usb_phy_init(struct platform_device *pdev, int type)
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{
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if (type == S5P_USB_PHY_HOST)
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return exynos4_usb_phy1_init(pdev);
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return -EINVAL;
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}
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int s5p_usb_phy_exit(struct platform_device *pdev, int type)
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{
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if (type == S5P_USB_PHY_HOST)
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return exynos4_usb_phy1_exit(pdev);
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return -EINVAL;
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}
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@ -45,6 +45,13 @@ struct platform_device s5p_device_ehci = {
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void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
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{
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s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
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struct s5p_ehci_platdata *npd;
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npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
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&s5p_device_ehci);
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if (!npd->phy_init)
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npd->phy_init = s5p_usb_phy_init;
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if (!npd->phy_exit)
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npd->phy_exit = s5p_usb_phy_exit;
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}
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@ -39,7 +39,7 @@
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#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
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#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
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#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
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#define S5P_VA_USB_HSPHY S3C_ADDR(0x02900000)
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#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
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#define VA_VIC0 VA_VIC(0)
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@ -0,0 +1,22 @@
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/*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Author: Joonyoung Shim <jy0922.shim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __PLAT_S5P_USB_PHY_H
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#define __PLAT_S5P_USB_PHY_H
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enum s5p_usb_phy_type {
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S5P_USB_PHY_DEVICE,
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S5P_USB_PHY_HOST,
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};
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extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
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extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
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#endif /* __PLAT_S5P_REGS_USB_PHY_H */
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