Merge branch 'omap_clock_fixes_3.2' of git://git.pwsan.com/linux-2.6 into fixes
This commit is contained in:
Tony Lindgren
Коммит
8f86f36284
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@ -46,10 +46,19 @@
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(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
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/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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#define DPLL_FINT_BAND1_MIN 750000
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#define DPLL_FINT_BAND1_MAX 2100000
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#define DPLL_FINT_BAND2_MIN 7500000
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#define DPLL_FINT_BAND2_MAX 21000000
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#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
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#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
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#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
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#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
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/*
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* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
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* From device data manual section 4.3 "DPLL and DLL Specifications".
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*/
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
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#define OMAP3PLUS_DPLL_FINT_MIN 32000
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#define OMAP3PLUS_DPLL_FINT_MAX 52000000
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/* _dpll_test_fint() return codes */
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#define DPLL_FINT_UNDERFLOW -1
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@ -71,33 +80,43 @@
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static int _dpll_test_fint(struct clk *clk, u8 n)
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{
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struct dpll_data *dd;
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long fint;
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long fint, fint_min, fint_max;
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int ret = 0;
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dd = clk->dpll_data;
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/* DPLL divider must result in a valid jitter correction val */
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fint = clk->parent->rate / n;
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if (fint < DPLL_FINT_BAND1_MIN) {
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if (cpu_is_omap24xx()) {
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/* Should not be called for OMAP2, so warn if it is called */
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WARN(1, "No fint limits available for OMAP2!\n");
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return DPLL_FINT_INVALID;
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} else if (cpu_is_omap3430()) {
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fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
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fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
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} else if (dd->flags & DPLL_J_TYPE) {
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fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
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} else {
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fint_min = OMAP3PLUS_DPLL_FINT_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_MAX;
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}
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if (fint < fint_min) {
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pr_debug("rejecting n=%d due to Fint failure, "
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"lowering max_divider\n", n);
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dd->max_divider = n;
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ret = DPLL_FINT_UNDERFLOW;
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} else if (fint > DPLL_FINT_BAND1_MAX &&
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fint < DPLL_FINT_BAND2_MIN) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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} else if (fint > DPLL_FINT_BAND2_MAX) {
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} else if (fint > fint_max) {
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pr_debug("rejecting n=%d due to Fint failure, "
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"boosting min_divider\n", n);
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dd->min_divider = n;
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ret = DPLL_FINT_INVALID;
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} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
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fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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}
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return ret;
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@ -66,6 +66,8 @@ void omap3_noncore_dpll_disable(struct clk *clk);
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int omap4_dpllmx_gatectrl_read(struct clk *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk *clk);
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void omap4_dpllmx_deny_gatectrl(struct clk *clk);
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long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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void omap2_clk_disable_unused(struct clk *clk);
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@ -8,6 +8,13 @@
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
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/*
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* OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is
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* set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM
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* vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters")
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*/
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#define OMAP4430_REGM4XEN_MULT 4
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int omap4xxx_clk_init(void);
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#endif
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@ -270,8 +270,8 @@ static struct clk dpll_abe_ck = {
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.dpll_data = &dpll_abe_dd,
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.init = &omap2_init_dpll_parent,
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.ops = &clkops_omap3_noncore_dpll_ops,
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.recalc = &omap3_dpll_recalc,
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.round_rate = &omap2_dpll_round_rate,
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.recalc = &omap4_dpll_regm4xen_recalc,
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.round_rate = &omap4_dpll_regm4xen_round_rate,
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.set_rate = &omap3_noncore_dpll_set_rate,
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};
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@ -1195,11 +1195,25 @@ static struct clk l4_wkup_clk_mux_ck = {
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.recalc = &omap2_clksel_recalc,
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};
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static const struct clksel_rate div2_2to1_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
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{ .div = 2, .val = 0, .flags = RATE_IN_4430 },
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{ .div = 0 },
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};
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static const struct clksel ocp_abe_iclk_div[] = {
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{ .parent = &aess_fclk, .rates = div2_2to1_rates },
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{ .parent = NULL },
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};
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static struct clk ocp_abe_iclk = {
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.name = "ocp_abe_iclk",
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.parent = &aess_fclk,
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.clksel = ocp_abe_iclk_div,
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.clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
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.clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
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.ops = &clkops_null,
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.recalc = &followparent_recalc,
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.recalc = &omap2_clksel_recalc,
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};
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static struct clk per_abe_24m_fclk = {
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@ -1398,9 +1412,9 @@ static struct clk dss_dss_clk = {
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};
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static const struct clksel_rate div3_8to32_rates[] = {
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{ .div = 8, .val = 0, .flags = RATE_IN_44XX },
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{ .div = 16, .val = 1, .flags = RATE_IN_44XX },
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{ .div = 32, .val = 2, .flags = RATE_IN_44XX },
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{ .div = 8, .val = 0, .flags = RATE_IN_4460 },
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{ .div = 16, .val = 1, .flags = RATE_IN_4460 },
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{ .div = 32, .val = 2, .flags = RATE_IN_4460 },
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{ .div = 0 },
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};
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@ -3403,12 +3417,12 @@ int __init omap4xxx_clk_init(void)
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struct omap_clk *c;
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u32 cpu_clkflg;
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if (cpu_is_omap44xx()) {
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if (cpu_is_omap443x()) {
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cpu_mask = RATE_IN_4430;
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cpu_clkflg = CK_443X;
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} else if (cpu_is_omap446x()) {
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cpu_mask = RATE_IN_4460;
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cpu_clkflg = CK_446X;
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cpu_mask = RATE_IN_4460 | RATE_IN_4430;
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cpu_clkflg = CK_446X | CK_443X;
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} else {
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return 0;
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}
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@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
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* propagating?
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*/
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if (!r)
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clk->rate = omap2_get_dpll_rate(clk);
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clk->rate = (clk->recalc) ? clk->recalc(clk) :
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omap2_get_dpll_rate(clk);
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return r;
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}
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@ -424,6 +425,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *new_parent = NULL;
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unsigned long hw_rate;
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u16 freqsel = 0;
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struct dpll_data *dd;
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int ret;
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@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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if (!dd)
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return -EINVAL;
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if (rate == omap2_get_dpll_rate(clk))
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hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
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if (rate == hw_rate)
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return 0;
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/*
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@ -455,7 +458,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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new_parent = dd->clk_bypass;
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} else {
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if (dd->last_rounded_rate != rate)
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omap2_dpll_round_rate(clk, rate);
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rate = clk->round_rate(clk, rate);
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if (dd->last_rounded_rate == 0)
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return -EINVAL;
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@ -19,6 +19,7 @@
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock44xx.h"
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#include "cm-regbits-44xx.h"
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/* Supported only on OMAP4 */
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@ -82,3 +83,71 @@ const struct clkops clkops_omap4_dpllmx_ops = {
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.deny_idle = omap4_dpllmx_deny_gatectrl,
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};
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/**
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* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
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* @clk: struct clk * of the DPLL to compute the rate for
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*
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* Compute the output rate for the OMAP4 DPLL represented by @clk.
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* Takes the REGM4XEN bit into consideration, which is needed for the
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* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
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* upon success, or 0 upon error.
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*/
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unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
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{
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u32 v;
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unsigned long rate;
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struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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return 0;
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dd = clk->dpll_data;
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rate = omap2_get_dpll_rate(clk);
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/* regm4xen adds a multiplier of 4 to DPLL calculations */
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v = __raw_readl(dd->control_reg);
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if (v & OMAP4430_DPLL_REGM4XEN_MASK)
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rate *= OMAP4430_REGM4XEN_MULT;
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return rate;
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}
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/**
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* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
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* @clk: struct clk * of the DPLL to round a rate for
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* @target_rate: the desired rate of the DPLL
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*
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* Compute the rate that would be programmed into the DPLL hardware
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* for @clk if set_rate() were to be provided with the rate
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* @target_rate. Takes the REGM4XEN bit into consideration, which is
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* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
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* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
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* ~0 if an error occurred in omap2_dpll_round_rate().
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*/
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long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
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{
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u32 v;
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struct dpll_data *dd;
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long r;
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if (!clk || !clk->dpll_data)
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return -EINVAL;
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dd = clk->dpll_data;
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/* regm4xen adds a multiplier of 4 to DPLL calculations */
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v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
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if (v)
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target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
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r = omap2_dpll_round_rate(clk, target_rate);
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if (r == ~0)
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return r;
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if (v)
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clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
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return clk->dpll_data->last_rounded_rate;
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}
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