mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
Now that all functions using that flag are local to the micron module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-26-michael@walle.cc
This commit is contained in:
Michael Walle
Tudor Ambarus
Родитель
c770abe52d
Коммит
8f938262a6
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@ -2499,9 +2499,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)
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if (flags & USE_CLSR)
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nor->flags |= SNOR_F_USE_CLSR;
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if (flags & USE_FSR)
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nor->flags |= SNOR_F_USE_FSR;
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}
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/**
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@ -12,7 +12,6 @@
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#define SPI_NOR_MAX_ID_LEN 6
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enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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SNOR_F_USE_CLSR = BIT(4),
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@ -349,7 +348,6 @@ struct spi_nor_fixups {
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* NO_CHIP_ERASE: chip does not support chip erase.
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* SPI_NOR_NO_FR: can't do fastread.
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* USE_CLSR: use CLSR command.
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* USE_FSR: use flag status register
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*
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* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
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* Used when SFDP tables are not defined in the flash. These
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@ -401,7 +399,6 @@ struct flash_info {
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#define NO_CHIP_ERASE BIT(7)
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#define SPI_NOR_NO_FR BIT(8)
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#define USE_CLSR BIT(9)
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#define USE_FSR BIT(10)
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u8 no_sfdp_flags;
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#define SPI_NOR_SKIP_SFDP BIT(0)
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@ -8,6 +8,9 @@
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#include "core.h"
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/* flash_info mfr_flag. Used to read proprietary FSR register. */
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#define USE_FSR BIT(0)
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
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#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
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@ -140,15 +143,17 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = {
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static const struct flash_info micron_nor_parts[] = {
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{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ |
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SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE)
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.fixups = &mt35xu512aba_fixups},
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MFR_FLAGS(USE_FSR)
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.fixups = &mt35xu512aba_fixups
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},
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{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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MFR_FLAGS(USE_FSR)
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},
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};
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static const struct flash_info st_nor_parts[] = {
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@ -164,57 +169,79 @@ static const struct flash_info st_nor_parts[] = {
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
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SPI_NOR_BP3_SR_BIT6 | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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SPI_NOR_BP3_SR_BIT6)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
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SPI_NOR_BP3_SR_BIT6 | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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SPI_NOR_BP3_SR_BIT6)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
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SPI_NOR_BP3_SR_BIT6 | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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SPI_NOR_BP3_SR_BIT6)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
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FLAGS(USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
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SPI_NOR_BP3_SR_BIT6 | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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SPI_NOR_BP3_SR_BIT6)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
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SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
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FLAGS(NO_CHIP_ERASE | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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FLAGS(NO_CHIP_ERASE)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
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FLAGS(NO_CHIP_ERASE | USE_FSR)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
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FLAGS(NO_CHIP_ERASE)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
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FLAGS(NO_CHIP_ERASE | USE_FSR)
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FLAGS(NO_CHIP_ERASE)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_FSR)
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},
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{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
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{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
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@ -410,7 +437,7 @@ static void micron_st_nor_default_init(struct spi_nor *nor)
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static void micron_st_nor_late_init(struct spi_nor *nor)
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{
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if (nor->flags & SNOR_F_USE_FSR)
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if (nor->info->mfr_flags & USE_FSR)
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nor->params->ready = spi_nor_fsr_ready;
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}
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