habanalabs: set TPC Icache to 16 cache lines
Reduce latency to memory during TPC kernel execution. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Reviewed-by: Tomer Tayar <ttayar@habana.ai>
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cb596aee88
Коммит
8fdacf2a53
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@ -1457,6 +1457,9 @@ static void goya_init_golden_registers(struct hl_device *hdev)
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1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
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WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
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1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
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WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
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ICACHE_FETCH_LINE_NUM, 2);
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}
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WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
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@ -1062,9 +1062,10 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
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#define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT
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#define REG_FIELD_MASK(reg, field) reg##_##field##_MASK
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#define WREG32_FIELD(reg, field, val) \
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WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \
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(val) << REG_FIELD_SHIFT(reg, field))
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#define WREG32_FIELD(reg, offset, field, val) \
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WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & \
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~REG_FIELD_MASK(reg, field)) | \
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(val) << REG_FIELD_SHIFT(reg, field))
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/* Timeout should be longer when working with simulator but cap the
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* increased timeout to some maximum
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