drm/nvc0/graph: fix fuc, and enable acceleration on GF119

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc

@@ -754,6 +754,16 @@ ctx_mmio_exec:
 //		on load it means: "a save preceeded this load"
 //
 ctx_xfer:
+	// according to mwk, some kind of wait for idle
+	mov $r15 0xc00
+	shl b32 $r15 6
+	mov $r14 4
+	iowr I[$r15 + 0x200] $r14
+	ctx_xfer_idle:
+		iord $r14 I[$r15 + 0x000]
+		and $r14 0x2000
+		bra ne #ctx_xfer_idle
+
 	bra not $p1 #ctx_xfer_pre
 	bra $p2 #ctx_xfer_pre_load
 	ctx_xfer_pre:

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h

@@ -799,79 +799,80 @@ uint32_t nvc0_grhub_code[] = {
 	0x01fa0613,
 	0xf803f806,
 /* 0x0829: ctx_xfer */
-	0x0611f400,
+	0x00f7f100,
-/* 0x082f: ctx_xfer_pre */
+	0x06f4b60c,
-	0xf01102f4,
+	0xd004e7f0,
-	0x21f510f7,
+/* 0x0836: ctx_xfer_idle */
-	0x21f50698,
+	0xfecf80fe,
-	0x11f40631,
+	0x00e4f100,
-/* 0x083d: ctx_xfer_pre_load */
+	0xf91bf420,
-	0x02f7f01c,
+	0xf40611f4,
-	0x065721f5,
+/* 0x0846: ctx_xfer_pre */
-	0x066621f5,
+	0xf7f01102,
-	0x067821f5,
+	0x9821f510,
-	0x21f5f4bd,
+	0x3121f506,
-	0x21f50657,
+	0x1c11f406,
-/* 0x0856: ctx_xfer_exec */
+/* 0x0854: ctx_xfer_pre_load */
-	0x019806b8,
+	0xf502f7f0,
-	0x1427f116,
+	0xf5065721,
-	0x0624b604,
+	0xf5066621,
-	0xf10020d0,
+	0xbd067821,
-	0xf0a500e7,
+	0x5721f5f4,
-	0x1fb941e3,
+	0xb821f506,
-	0x8d21f402,
+/* 0x086d: ctx_xfer_exec */
-	0xf004e0b6,
+	0x16019806,
-	0x2cf001fc,
+	0x041427f1,
-	0x0124b602,
+	0xd00624b6,
-	0xf405f2fd,
+	0xe7f10020,
-	0x17f18d21,
+	0xe3f0a500,
-	0x13f04afc,
+	0x021fb941,
-	0x0c27f002,
+	0xb68d21f4,
-	0xf50012d0,
+	0xfcf004e0,
-	0xf1020721,
+	0x022cf001,
-	0xf047fc27,
+	0xfd0124b6,
-	0x20d00223,
+	0x21f405f2,
-	0x012cf000,
+	0xfc17f18d,
-	0xd00320b6,
+	0x0213f04a,
-	0xacf00012,
+	0xd00c27f0,
-	0x06a5f001,
+	0x21f50012,
-	0x9800b7f0,
+	0x27f10207,
-	0x0d98140c,
+	0x23f047fc,
-	0x00e7f015,
+	0x0020d002,
-	0x015c21f5,
+	0xb6012cf0,
-	0xf508a7f0,
+	0x12d00320,
-	0xf5010321,
+	0x01acf000,
-	0xf4020721,
+	0xf006a5f0,
-	0xa7f02201,
+	0x0c9800b7,
-	0xc921f40c,
+	0x150d9814,
-	0x0a1017f1,
+	0xf500e7f0,
-	0xf00614b6,
+	0xf0015c21,
-	0x12d00527,
+	0x21f508a7,
-/* 0x08dd: ctx_xfer_post_save_wait */
+	0x21f50103,
-	0x0012cf00,
+	0x01f40207,
-	0xf40522fd,
+	0x0ca7f022,
-	0x02f4fa1b,
+	0xf1c921f4,
-/* 0x08e9: ctx_xfer_post */
+	0xb60a1017,
-	0x02f7f032,
+	0x27f00614,
-	0x065721f5,
+	0x0012d005,
-	0x21f5f4bd,
+/* 0x08f4: ctx_xfer_post_save_wait */
-	0x21f50698,
+	0xfd0012cf,
-	0x21f50226,
+	0x1bf40522,
-	0xf4bd0666,
+	0x3202f4fa,
-	0x065721f5,
+/* 0x0900: ctx_xfer_post */
-	0x981011f4,
+	0xf502f7f0,
-	0x11fd8001,
+	0xbd065721,
-	0x070bf405,
+	0x9821f5f4,
-	0x07df21f5,
+	0x2621f506,
-/* 0x0914: ctx_xfer_no_post_mmio */
+	0x6621f502,
-	0x064921f5,
+	0xf5f4bd06,
-/* 0x0918: ctx_xfer_done */
+	0xf4065721,
-	0x000000f8,
+	0x01981011,
-	0x00000000,
+	0x0511fd80,
-	0x00000000,
+	0xf5070bf4,
-	0x00000000,
+/* 0x092b: ctx_xfer_no_post_mmio */
-	0x00000000,
+	0xf507df21,
-	0x00000000,
+/* 0x092f: ctx_xfer_done */
+	0xf8064921,
 	0x00000000,
 	0x00000000,
 	0x00000000,

drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c

@@ -516,18 +516,9 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 {
 	struct nouveau_device *device = nv_device(parent);
 	struct nvc0_graph_priv *priv;
-	bool enable = true;
 	int ret, i;
 
-	switch (device->chipset) {
+	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-	case 0xd9: /* known broken without binary driver firmware */
-		enable = false;
-		break;
-	default:
-		break;
-	}
-
-	ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;