clk: mediatek: mt8365: Convert simple_gate to mtk_gate clocks
On this SoC some clocks apparently don't have different offsets for set/clr/sta registers hence they can be set, cleared and status-read on one register: this means that it was possible to use simpler gate clocks instead of custom mtk_gate ones. In preparation for converting this clock driver to the common probe mechanism for MediaTek clocks, perform a conversion from simple_gate to mtk_gate clocks since the latter does provide implicit support for simple gate clocks as well. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-13-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
Родитель
ab44c1a70e
Коммит
905b7430d3
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@ -1,6 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Copyright (C) 2023 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8365-clk.h>
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@ -393,12 +395,6 @@ static struct mtk_composite top_misc_mux_gates[] = {
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0x0ec, 0, 2, 7),
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};
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struct mt8365_clk_audio_mux {
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int id;
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const char *name;
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u8 shift;
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};
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static struct mt8365_clk_audio_mux top_misc_muxes[] = {
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{ CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11},
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{ CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12},
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@ -569,35 +565,56 @@ static const struct mtk_clk_divider top_adj_divs[] = {
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0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
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};
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struct mtk_simple_gate {
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int id;
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const char *name;
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const char *parent;
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u32 reg;
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u8 shift;
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unsigned long gate_flags;
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static const struct mtk_gate_regs top0_cg_regs = {
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.set_ofs = 0,
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.clr_ofs = 0,
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.sta_ofs = 0,
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};
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static const struct mtk_simple_gate top_clk_gates[] = {
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{ CLK_TOP_CONN_32K, "conn_32k", "clk32k", 0x0, 10, CLK_GATE_SET_TO_DISABLE },
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{ CLK_TOP_CONN_26M, "conn_26m", "clk26m", 0x0, 11, CLK_GATE_SET_TO_DISABLE },
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{ CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 0x0, 16, CLK_GATE_SET_TO_DISABLE },
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{ CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 0x0, 17, CLK_GATE_SET_TO_DISABLE },
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{ CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 0x104, 8, 0 },
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{ CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 0x104, 9, 0 },
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{ CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 0x104, 20, 0 },
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{ CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 0x104, 21, 0 },
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{ CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 0x104, 22, 0 },
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{ CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 0x104, 23, 0 },
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{ CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0x320, 0, 0 },
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{ CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 0x320, 1, 0 },
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{ CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 0x320, 2, 0 },
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{ CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 0x320, 3, 0 },
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{ CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 0x320, 4, 0 },
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{ CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 0x320, 5, 0 },
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{ CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 0x320, 6, 0 },
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{ CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 0x320, 7, 0 },
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{ CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 0x320, 8, 0 },
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static const struct mtk_gate_regs top1_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x104,
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.sta_ofs = 0x104,
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};
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static const struct mtk_gate_regs top2_cg_regs = {
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.set_ofs = 0x320,
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.clr_ofs = 0x320,
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.sta_ofs = 0x320,
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};
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#define GATE_TOP0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &top0_cg_regs, \
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_shift, &mtk_clk_gate_ops_no_setclr_inv)
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#define GATE_TOP1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &top1_cg_regs, \
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_shift, &mtk_clk_gate_ops_no_setclr)
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#define GATE_TOP2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &top2_cg_regs, \
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_shift, &mtk_clk_gate_ops_no_setclr)
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static const struct mtk_gate top_clk_gates[] = {
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GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
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GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11),
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GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16),
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GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17),
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GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8),
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GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9),
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GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20),
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GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21),
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GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22),
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GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23),
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GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
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GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
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GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
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GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
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GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
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GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5),
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GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
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GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
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GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
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};
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static const struct mtk_gate_regs ifr2_cg_regs = {
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@ -630,50 +647,24 @@ static const struct mtk_gate_regs ifr6_cg_regs = {
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.sta_ofs = 0xd8,
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};
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#define GATE_IFR2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_IFRX(_id, _name, _parent, _shift, _regs) \
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GATE_MTK(_id, _name, _parent, _regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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#define GATE_IFR3(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr3_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_IFR2(_id, _name, _parent, _shift) \
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GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs)
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#define GATE_IFR4(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr4_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_IFR3(_id, _name, _parent, _shift) \
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GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs)
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#define GATE_IFR5(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr5_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_IFR4(_id, _name, _parent, _shift) \
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GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs)
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#define GATE_IFR6(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr6_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_IFR5(_id, _name, _parent, _shift) \
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GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs)
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#define GATE_IFR6(_id, _name, _parent, _shift) \
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GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs)
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static const struct mtk_gate ifr_clks[] = {
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/* IFR2 */
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@ -752,33 +743,16 @@ static const struct mtk_gate ifr_clks[] = {
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GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11),
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};
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static const struct mtk_simple_gate peri_clks[] = {
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{ CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 },
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static const struct mtk_gate_regs peri_cg_regs = {
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.set_ofs = 0x20c,
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.clr_ofs = 0x20c,
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.sta_ofs = 0x20c,
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};
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static int
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clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *base,
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struct clk_hw_onecell_data *clk_data,
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const struct mtk_simple_gate *gates,
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unsigned int num_gates)
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{
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unsigned int i;
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for (i = 0; i != num_gates; ++i) {
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const struct mtk_simple_gate *gate = &gates[i];
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struct clk_hw *hw;
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hw = devm_clk_hw_register_gate(dev, gate->name, gate->parent, 0,
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base + gate->reg, gate->shift,
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gate->gate_flags, NULL);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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clk_data->hws[gate->id] = hw;
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}
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return 0;
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}
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static const struct mtk_gate peri_clks[] = {
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GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31,
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&mtk_clk_gate_ops_no_setclr),
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};
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static int clk_mt8365_top_probe(struct platform_device *pdev)
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{
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@ -840,17 +814,18 @@ static int clk_mt8365_top_probe(struct platform_device *pdev)
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if (ret)
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goto unregister_composites;
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ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data,
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top_clk_gates,
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ARRAY_SIZE(top_clk_gates));
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ret = mtk_clk_register_gates(&pdev->dev, node, top_clk_gates,
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ARRAY_SIZE(top_clk_gates), clk_data);
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if (ret)
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goto unregister_dividers;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_dividers;
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goto unregister_gates;
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return 0;
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unregister_gates:
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mtk_clk_unregister_gates(top_clk_gates, ARRAY_SIZE(top_clk_gates), clk_data);
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unregister_dividers:
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mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
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clk_data);
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@ -915,9 +890,9 @@ static int clk_mt8365_peri_probe(struct platform_device *pdev)
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if (!clk_data)
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return -ENOMEM;
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ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data,
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peri_clks,
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ARRAY_SIZE(peri_clks));
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ret = mtk_clk_register_gates(&pdev->dev, node, peri_clks,
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ARRAY_SIZE(peri_clks), clk_data);
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if (ret)
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return ret;
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