clk: meson: meson8b: add the video decoder clock trees
This adds the four video decoder clock trees.
VDEC_1 is split into two paths on Meson8b and Meson8m2:
- input mux called "vdec_1_sel"
- two dividers ("vdec_1_1_div" and "vdec_1_2_div") and gates ("vdec_1_1"
and "vdec_1_2")
- and an output mux (probably glitch-free) called "vdec_1"
On Meson8 the VDEC_1 tree is simpler because there's only one path:
- input mux called "vdec_1_sel"
- divider ("vdec_1_1_div") and gate ("vdec_1_1")
- (the gate is used as output directly, there's no mux)
The VDEC_HCODEC and VDEC_2 clocks are simple composite clocks each
consisting of an input mux, divider and a gate.
The VDEC_HEVC clock seems to have two paths similar to the VDEC_1 clock.
However, the register offsets of the second clock path is not known.
Amlogic's 3.10 kernel (which is used as reference) sets
HHI_VDEC2_CLK_CNTL[31] to 1 before changing the VDEC_HEVC clock and back
to 0 afterwards. For now, leave a TODO comment and only add the first
path.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190324151423.19063-3-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl
Neil Armstrong
Родитель
41785ce562
Коммит
90751f686e
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@ -1902,6 +1902,257 @@ static struct clk_regmap meson8b_vpu = {
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},
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};
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static const char * const meson8b_vdec_parent_names[] = {
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"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
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};
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static struct clk_regmap meson8b_vdec_1_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = meson8b_vdec_parent_names,
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.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_1_1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1_1_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_1_1 = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_1_1",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_1_1_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_1_2_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC3_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1_2_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_1_2 = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC3_CLK_CNTL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_1_2",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_1_2_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_1 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC3_CLK_CNTL,
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.mask = 0x1,
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.shift = 15,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hcodec_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.mask = 0x3,
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.shift = 25,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hcodec_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = meson8b_vdec_parent_names,
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.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hcodec_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hcodec_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_hcodec_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hcodec = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_hcodec",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_hcodec_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_2_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_2_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = meson8b_vdec_parent_names,
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.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_2_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_2_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_2_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_2 = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_2",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_2_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hevc_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.mask = 0x3,
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.shift = 25,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevc_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = meson8b_vdec_parent_names,
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.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hevc_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevc_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_hevc_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hevc_en = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_hevc_en",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_hevc_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vdec_hevc = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.mask = 0x1,
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.shift = 31,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevc",
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.ops = &clk_regmap_mux_ops,
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/* TODO: The second parent is currently unknown */
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.parent_names = (const char *[]){ "vdec_hevc_en" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
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@ -2168,6 +2419,19 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
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[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
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[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
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[CLKID_VPU] = &meson8b_vpu_0.hw,
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[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
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[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
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[CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
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[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
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[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
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[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
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[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
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[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
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[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
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[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
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[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
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[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
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[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2361,6 +2625,22 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
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[CLKID_VPU_1] = &meson8b_vpu_1.hw,
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[CLKID_VPU] = &meson8b_vpu.hw,
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[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
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[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
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[CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
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[CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
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[CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
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[CLKID_VDEC_1] = &meson8b_vdec_1.hw,
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[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
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[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
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[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
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[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
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[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
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[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
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[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
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[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
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[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
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[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2556,6 +2836,22 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
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[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
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[CLKID_VPU_1] = &meson8b_vpu_1.hw,
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[CLKID_VPU] = &meson8b_vpu.hw,
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[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
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[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
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[CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
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[CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
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[CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
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[CLKID_VDEC_1] = &meson8b_vdec_1.hw,
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[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
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[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
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[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
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[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
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[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
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[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
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[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
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[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
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[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
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[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2729,6 +3025,22 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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&meson8b_vpu_1_div,
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&meson8b_vpu_1,
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&meson8b_vpu,
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&meson8b_vdec_1_sel,
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&meson8b_vdec_1_1_div,
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&meson8b_vdec_1_1,
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&meson8b_vdec_1_2_div,
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&meson8b_vdec_1_2,
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&meson8b_vdec_1,
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&meson8b_vdec_hcodec_sel,
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&meson8b_vdec_hcodec_div,
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&meson8b_vdec_hcodec,
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&meson8b_vdec_2_sel,
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&meson8b_vdec_2_div,
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&meson8b_vdec_2,
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&meson8b_vdec_hevc_sel,
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&meson8b_vdec_hevc_div,
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&meson8b_vdec_hevc_en,
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&meson8b_vdec_hevc,
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};
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static const struct meson8b_clk_reset_line {
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@ -37,6 +37,9 @@
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#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
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#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
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#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
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#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
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#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
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#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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@ -156,8 +159,20 @@
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#define CLKID_VPU_1_SEL 186
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#define CLKID_VPU_1_DIV 187
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#define CLKID_VPU_1 189
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#define CLKID_VDEC_1_SEL 191
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#define CLKID_VDEC_1_1_DIV 192
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#define CLKID_VDEC_1_1 193
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#define CLKID_VDEC_1_2_DIV 194
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#define CLKID_VDEC_1_2 195
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#define CLKID_VDEC_HCODEC_SEL 197
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#define CLKID_VDEC_HCODEC_DIV 198
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#define CLKID_VDEC_2_SEL 200
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#define CLKID_VDEC_2_DIV 201
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#define CLKID_VDEC_HEVC_SEL 203
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#define CLKID_VDEC_HEVC_DIV 204
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#define CLKID_VDEC_HEVC_EN 205
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#define CLK_NR_CLKS 191
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#define CLK_NR_CLKS 207
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/*
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* include the CLKID and RESETID that have
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