drm/radeon: fix dpm mc init for certain hawaii boards
Needs special overrides for certain vram configurations. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4e21518c3d
Коммит
90b2fee35c
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@ -4099,6 +4099,96 @@ static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
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return 0;
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}
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static int ci_register_patching_mc_seq(struct radeon_device *rdev,
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struct ci_mc_reg_table *table)
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{
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u8 i, k;
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u32 tmp;
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bool patch;
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tmp = RREG32(MC_SEQ_MISC0);
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patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
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if (patch &&
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((rdev->pdev->device == 0x67B0) ||
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(rdev->pdev->device == 0x67B1))) {
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for (i = 0; i < table->last; i++) {
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if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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switch(table->mc_reg_address[i].s1 >> 2) {
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case MC_SEQ_MISC1:
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for (k = 0; k < table->num_entries; k++) {
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if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
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(table->mc_reg_table_entry[k].mclk_max == 137500))
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
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0x00000007;
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}
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break;
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case MC_SEQ_WR_CTL_D0:
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for (k = 0; k < table->num_entries; k++) {
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if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
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(table->mc_reg_table_entry[k].mclk_max == 137500))
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
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0x0000D0DD;
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}
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break;
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case MC_SEQ_WR_CTL_D1:
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for (k = 0; k < table->num_entries; k++) {
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if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
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(table->mc_reg_table_entry[k].mclk_max == 137500))
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
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0x0000D0DD;
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}
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break;
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case MC_SEQ_WR_CTL_2:
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for (k = 0; k < table->num_entries; k++) {
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if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
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(table->mc_reg_table_entry[k].mclk_max == 137500))
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table->mc_reg_table_entry[k].mc_data[i] = 0;
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}
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break;
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case MC_SEQ_CAS_TIMING:
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for (k = 0; k < table->num_entries; k++) {
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if (table->mc_reg_table_entry[k].mclk_max == 125000)
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
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0x000C0140;
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else if (table->mc_reg_table_entry[k].mclk_max == 137500)
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
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0x000C0150;
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}
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break;
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case MC_SEQ_MISC_TIMING:
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for (k = 0; k < table->num_entries; k++) {
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if (table->mc_reg_table_entry[k].mclk_max == 125000)
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
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0x00000030;
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else if (table->mc_reg_table_entry[k].mclk_max == 137500)
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table->mc_reg_table_entry[k].mc_data[i] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
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0x00000035;
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}
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break;
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default:
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break;
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}
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}
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WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
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tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
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tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
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WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
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WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
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}
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return 0;
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}
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static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
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{
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struct ci_power_info *pi = ci_get_pi(rdev);
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@ -4142,6 +4232,10 @@ static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
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ci_set_s0_mc_reg_index(ci_table);
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ret = ci_register_patching_mc_seq(rdev, ci_table);
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if (ret)
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goto init_mc_done;
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ret = ci_set_mc_special_registers(rdev, ci_table);
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if (ret)
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goto init_mc_done;
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