intel-gtt: generic (insert|remove)_entries for sandybridge
Like before, but now with the added bonus of being able to kill quite a bit of no-longer userful code (the old dmar support stuff). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Daniel Vetter
Chris Wilson
Родитель
450f2b3d51
Коммит
90cb149e1a
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@ -177,61 +177,6 @@ static void intel_agp_unmap_memory(struct agp_memory *mem)
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intel_agp_free_sglist(mem);
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}
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#if USE_PCI_DMA_API
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static void intel_agp_insert_sg_entries(struct agp_memory *mem,
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off_t pg_start, int mask_type)
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{
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struct scatterlist *sg;
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int i, j;
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j = pg_start;
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WARN_ON(!mem->num_sg);
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if (mem->num_sg == mem->page_count) {
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for_each_sg(mem->sg_list, sg, mem->page_count, i) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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sg_dma_address(sg), mask_type),
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intel_private.gtt+j);
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j++;
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}
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} else {
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/* sg may merge pages, but we have to separate
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* per-page addr for GTT */
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unsigned int len, m;
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for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
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len = sg_dma_len(sg) / PAGE_SIZE;
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for (m = 0; m < len; m++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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sg_dma_address(sg) + m * PAGE_SIZE,
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mask_type),
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intel_private.gtt+j);
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j++;
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}
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}
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}
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readl(intel_private.gtt+j-1);
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}
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#else
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static void intel_agp_insert_sg_entries(struct agp_memory *mem,
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off_t pg_start, int mask_type)
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{
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int i, j;
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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page_to_phys(mem->pages[i]), mask_type),
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intel_private.gtt+j);
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}
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readl(intel_private.gtt+j-1);
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}
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#endif
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static int intel_i810_fetch_size(void)
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{
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u32 smram_miscc;
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@ -1266,81 +1211,6 @@ static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
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writel(1, intel_private.i9xx_flush_page);
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}
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static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int num_entries;
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void *temp;
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int ret = -EINVAL;
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int mask_type;
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if (mem->page_count == 0)
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goto out;
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temp = agp_bridge->current_size;
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num_entries = A_SIZE_FIX(temp)->num_entries;
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if (pg_start < intel_private.base.gtt_stolen_entries) {
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dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
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"pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
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pg_start, intel_private.base.gtt_stolen_entries);
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dev_info(&intel_private.pcidev->dev,
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"trying to insert into local/stolen memory\n");
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goto out_err;
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}
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if ((pg_start + mem->page_count) > num_entries)
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goto out_err;
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/* The i915 can't check the GTT for entries since it's read only;
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* depend on the caller to make the correct offset decisions.
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*/
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if (type != mem->type)
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goto out_err;
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mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
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if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
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mask_type != AGP_PHYS_MEMORY &&
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mask_type != INTEL_AGP_CACHED_MEMORY)
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goto out_err;
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if (!mem->is_flushed)
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global_cache_flush();
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intel_agp_insert_sg_entries(mem, pg_start, mask_type);
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out:
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ret = 0;
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out_err:
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mem->is_flushed = true;
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return ret;
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}
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static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int i;
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if (mem->page_count == 0)
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return 0;
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if (pg_start < intel_private.base.gtt_stolen_entries) {
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dev_info(&intel_private.pcidev->dev,
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"trying to disable local/stolen memory\n");
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return -EINVAL;
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}
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for (i = pg_start; i < (mem->page_count + pg_start); i++)
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writel(agp_bridge->scratch_page, intel_private.gtt+i);
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readl(intel_private.gtt+i-1);
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return 0;
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}
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static void i965_write_entry(dma_addr_t addr, unsigned int entry,
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unsigned int flags)
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{
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@ -1349,6 +1219,11 @@ static void i965_write_entry(dma_addr_t addr, unsigned int entry,
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writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
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}
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static bool gen6_check_flags(unsigned int flags)
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{
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return true;
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}
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static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
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unsigned int flags)
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{
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@ -1562,8 +1437,8 @@ static const struct agp_bridge_driver intel_gen6_driver = {
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.cache_flush = global_cache_flush,
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.create_gatt_table = intel_fake_agp_create_gatt_table,
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.free_gatt_table = intel_fake_agp_free_gatt_table,
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.insert_memory = intel_i915_insert_entries,
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.remove_memory = intel_i915_remove_entries,
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.insert_memory = intel_fake_agp_insert_entries,
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.remove_memory = intel_fake_agp_remove_entries,
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.alloc_by_type = intel_fake_agp_alloc_by_type,
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.free_by_type = intel_i810_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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@ -1572,10 +1447,6 @@ static const struct agp_bridge_driver intel_gen6_driver = {
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = intel_gen6_type_to_mask_type,
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.chipset_flush = intel_i915_chipset_flush,
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#if USE_PCI_DMA_API
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.agp_map_memory = intel_agp_map_memory,
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.agp_unmap_memory = intel_agp_unmap_memory,
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#endif
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};
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static const struct agp_bridge_driver intel_g33_driver = {
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@ -1654,6 +1525,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
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.gen = 6,
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.setup = i9xx_setup,
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.write_entry = gen6_write_entry,
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.check_flags = gen6_check_flags,
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};
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/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
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