Merge branch 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next
1. Fixing PLL regressions 2. A couple of memory reclocking and DPM fixes 3. Small cleanups * 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux: drm/radeon/ci: make sure mc ucode is loaded before checking the size drm/radeon/si: make sure mc ucode is loaded before checking the size drm/radeon: improve PLL params if we don't match exactly v2 drm/radeon: memory leak on bo reservation failure. v2 drm/radeon: fix VCE fence command drm/radeon: re-enable mclk dpm on R7 260X asics drm/radeon: add support for newer mc ucode on CI (v2) drm/radeon: add support for newer mc ucode on SI (v2) drm/radeon: apply more strict limits for PLL params v2 drm/radeon: update CI DPM powertune settings drm/radeon: fix runpm handling on APUs (v4) drm/radeon: disable mclk dpm on R7 260X
This commit is contained in:
Коммит
90e48970c2
|
@ -21,8 +21,10 @@
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*
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "radeon.h"
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#include "radeon_ucode.h"
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#include "cikd.h"
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#include "r600_dpm.h"
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#include "ci_dpm.h"
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@ -202,24 +204,29 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
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struct ci_power_info *pi = ci_get_pi(rdev);
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switch (rdev->pdev->device) {
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case 0x6649:
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case 0x6650:
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case 0x6651:
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case 0x6658:
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case 0x665C:
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case 0x665D:
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default:
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pi->powertune_defaults = &defaults_bonaire_xt;
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break;
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case 0x6651:
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case 0x665D:
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pi->powertune_defaults = &defaults_bonaire_pro;
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break;
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case 0x6640:
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pi->powertune_defaults = &defaults_saturn_xt;
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break;
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case 0x6641:
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pi->powertune_defaults = &defaults_saturn_pro;
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case 0x6646:
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case 0x6647:
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pi->powertune_defaults = &defaults_saturn_xt;
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break;
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case 0x67B8:
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case 0x67B0:
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pi->powertune_defaults = &defaults_hawaii_xt;
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break;
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case 0x67BA:
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case 0x67B1:
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pi->powertune_defaults = &defaults_hawaii_pro;
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break;
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case 0x67A0:
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case 0x67A1:
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case 0x67A2:
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@ -228,11 +235,7 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
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case 0x67AA:
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case 0x67B9:
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case 0x67BE:
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pi->powertune_defaults = &defaults_hawaii_xt;
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break;
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case 0x67BA:
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case 0x67B1:
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pi->powertune_defaults = &defaults_hawaii_pro;
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pi->powertune_defaults = &defaults_bonaire_xt;
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break;
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}
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@ -5146,6 +5149,12 @@ int ci_dpm_init(struct radeon_device *rdev)
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pi->mclk_dpm_key_disabled = 0;
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pi->pcie_dpm_key_disabled = 0;
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/* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
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if ((rdev->pdev->device == 0x6658) &&
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(rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
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pi->mclk_dpm_key_disabled = 1;
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}
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pi->caps_sclk_ds = true;
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pi->mclk_strobe_mode_threshold = 40000;
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|
|
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@ -38,6 +38,7 @@ MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
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MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
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@ -46,6 +47,7 @@ MODULE_FIRMWARE("radeon/HAWAII_me.bin");
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MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
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MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
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MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
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MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
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MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
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MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
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MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
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|
@ -1703,20 +1705,20 @@ int ci_mc_load_microcode(struct radeon_device *rdev)
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const __be32 *fw_data;
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u32 running, blackout = 0;
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u32 *io_mc_regs;
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int i, ucode_size, regs_size;
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int i, regs_size, ucode_size;
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if (!rdev->mc_fw)
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return -EINVAL;
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|
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ucode_size = rdev->mc_fw->size / 4;
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|
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switch (rdev->family) {
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case CHIP_BONAIRE:
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io_mc_regs = (u32 *)&bonaire_io_mc_regs;
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ucode_size = CIK_MC_UCODE_SIZE;
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regs_size = BONAIRE_IO_MC_REGS_SIZE;
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break;
|
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case CHIP_HAWAII:
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io_mc_regs = (u32 *)&hawaii_io_mc_regs;
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ucode_size = HAWAII_MC_UCODE_SIZE;
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regs_size = HAWAII_IO_MC_REGS_SIZE;
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break;
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default:
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|
@ -1783,7 +1785,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
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const char *chip_name;
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size_t pfp_req_size, me_req_size, ce_req_size,
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mec_req_size, rlc_req_size, mc_req_size = 0,
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sdma_req_size, smc_req_size = 0;
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sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
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char fw_name[30];
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int err;
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|
@ -1797,7 +1799,8 @@ static int cik_init_microcode(struct radeon_device *rdev)
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ce_req_size = CIK_CE_UCODE_SIZE * 4;
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mec_req_size = CIK_MEC_UCODE_SIZE * 4;
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rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
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mc_req_size = CIK_MC_UCODE_SIZE * 4;
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mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
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mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
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sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
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smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
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break;
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|
@ -1809,6 +1812,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
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mec_req_size = CIK_MEC_UCODE_SIZE * 4;
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rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
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mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
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mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
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sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
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smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
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break;
|
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|
@ -1904,16 +1908,22 @@ static int cik_init_microcode(struct radeon_device *rdev)
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|||
|
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/* No SMC, MC ucode on APUs */
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if (!(rdev->flags & RADEON_IS_IGP)) {
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snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
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snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
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err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
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if (err)
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goto out;
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if (rdev->mc_fw->size != mc_req_size) {
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if (err) {
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snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
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err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
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if (err)
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goto out;
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}
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if ((rdev->mc_fw->size != mc_req_size) &&
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(rdev->mc_fw->size != mc2_req_size)){
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printk(KERN_ERR
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"cik_mc: Bogus length %zu in firmware \"%s\"\n",
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rdev->mc_fw->size, fw_name);
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err = -EINVAL;
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}
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DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
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snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
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err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
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|
|
|
@ -2321,6 +2321,7 @@ struct radeon_device {
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bool have_disp_power_ref;
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};
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bool radeon_is_px(struct drm_device *dev);
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int radeon_device_init(struct radeon_device *rdev,
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struct drm_device *ddev,
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struct pci_dev *pdev,
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|
|
|
@ -59,7 +59,7 @@ struct atpx_mux {
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u16 mux;
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} __packed;
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bool radeon_is_px(void) {
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bool radeon_has_atpx(void) {
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return radeon_atpx_priv.atpx_detected;
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}
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|
|
|
@ -102,11 +102,14 @@ static const char radeon_family_name[][16] = {
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"LAST",
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};
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#if defined(CONFIG_VGA_SWITCHEROO)
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bool radeon_is_px(void);
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#else
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static inline bool radeon_is_px(void) { return false; }
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#endif
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bool radeon_is_px(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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|
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if (rdev->flags & RADEON_IS_PX)
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return true;
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return false;
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}
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/**
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* radeon_program_register_sequence - program an array of registers.
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|
@ -1082,7 +1085,7 @@ static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
|
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{
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struct drm_device *dev = pci_get_drvdata(pdev);
|
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|
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if (radeon_is_px() && state == VGA_SWITCHEROO_OFF)
|
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if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
|
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return;
|
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|
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if (state == VGA_SWITCHEROO_ON) {
|
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|
@ -1301,9 +1304,7 @@ int radeon_device_init(struct radeon_device *rdev,
|
|||
* ignore it */
|
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vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
|
||||
|
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if (radeon_runtime_pm == 1)
|
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runtime = true;
|
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if ((radeon_runtime_pm == -1) && radeon_is_px())
|
||||
if (rdev->flags & RADEON_IS_PX)
|
||||
runtime = true;
|
||||
vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
|
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if (runtime)
|
||||
|
|
|
@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
|
|||
unsigned post_div_min, post_div_max, post_div;
|
||||
unsigned ref_div_min, ref_div_max, ref_div;
|
||||
unsigned post_div_best, diff_best;
|
||||
unsigned nom, den, tmp;
|
||||
unsigned nom, den;
|
||||
|
||||
/* determine allowed feedback divider range */
|
||||
fb_div_min = pll->min_feedback_div;
|
||||
|
@ -937,23 +937,27 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
|
|||
}
|
||||
post_div = post_div_best;
|
||||
|
||||
/* limit reference * post divider to a maximum */
|
||||
ref_div_max = min(210 / post_div, ref_div_max);
|
||||
|
||||
/* get matching reference and feedback divider */
|
||||
ref_div = max(den / post_div, 1u);
|
||||
fb_div = nom;
|
||||
ref_div = max(DIV_ROUND_CLOSEST(den, post_div), 1u);
|
||||
fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
|
||||
|
||||
/* we're almost done, but reference and feedback
|
||||
divider might be to large now */
|
||||
|
||||
tmp = ref_div;
|
||||
nom = fb_div;
|
||||
den = ref_div;
|
||||
|
||||
if (fb_div > fb_div_max) {
|
||||
ref_div = ref_div * fb_div_max / fb_div;
|
||||
ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
|
||||
fb_div = fb_div_max;
|
||||
}
|
||||
|
||||
if (ref_div > ref_div_max) {
|
||||
ref_div = ref_div_max;
|
||||
fb_div = nom * ref_div_max / tmp;
|
||||
fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
|
||||
}
|
||||
|
||||
/* reduce the numbers to a simpler ratio once more */
|
||||
|
|
|
@ -115,6 +115,7 @@ extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
|
|||
unsigned int flags,
|
||||
int *vpos, int *hpos, ktime_t *stime,
|
||||
ktime_t *etime);
|
||||
extern bool radeon_is_px(struct drm_device *dev);
|
||||
extern const struct drm_ioctl_desc radeon_ioctls_kms[];
|
||||
extern int radeon_max_kms_ioctl;
|
||||
int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
|
||||
|
@ -144,11 +145,9 @@ void radeon_debugfs_cleanup(struct drm_minor *minor);
|
|||
#if defined(CONFIG_VGA_SWITCHEROO)
|
||||
void radeon_register_atpx_handler(void);
|
||||
void radeon_unregister_atpx_handler(void);
|
||||
bool radeon_is_px(void);
|
||||
#else
|
||||
static inline void radeon_register_atpx_handler(void) {}
|
||||
static inline void radeon_unregister_atpx_handler(void) {}
|
||||
static inline bool radeon_is_px(void) { return false; }
|
||||
#endif
|
||||
|
||||
int radeon_no_wb;
|
||||
|
@ -405,12 +404,7 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
|
|||
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
if (radeon_runtime_pm == 0) {
|
||||
pm_runtime_forbid(dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (radeon_runtime_pm == -1 && !radeon_is_px()) {
|
||||
if (!radeon_is_px(drm_dev)) {
|
||||
pm_runtime_forbid(dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
@ -434,10 +428,7 @@ static int radeon_pmops_runtime_resume(struct device *dev)
|
|||
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
if (radeon_runtime_pm == 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (radeon_runtime_pm == -1 && !radeon_is_px())
|
||||
if (!radeon_is_px(drm_dev))
|
||||
return -EINVAL;
|
||||
|
||||
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
||||
|
@ -462,14 +453,7 @@ static int radeon_pmops_runtime_idle(struct device *dev)
|
|||
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
||||
struct drm_crtc *crtc;
|
||||
|
||||
if (radeon_runtime_pm == 0) {
|
||||
pm_runtime_forbid(dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* are we PX enabled? */
|
||||
if (radeon_runtime_pm == -1 && !radeon_is_px()) {
|
||||
DRM_DEBUG_DRIVER("failing to power off - not px\n");
|
||||
if (!radeon_is_px(drm_dev)) {
|
||||
pm_runtime_forbid(dev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
|
|
@ -115,6 +115,7 @@ enum radeon_chip_flags {
|
|||
RADEON_NEW_MEMMAP = 0x00400000UL,
|
||||
RADEON_IS_PCI = 0x00800000UL,
|
||||
RADEON_IS_IGPGART = 0x01000000UL,
|
||||
RADEON_IS_PX = 0x02000000UL,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -35,9 +35,9 @@
|
|||
#include <linux/pm_runtime.h>
|
||||
|
||||
#if defined(CONFIG_VGA_SWITCHEROO)
|
||||
bool radeon_is_px(void);
|
||||
bool radeon_has_atpx(void);
|
||||
#else
|
||||
static inline bool radeon_is_px(void) { return false; }
|
||||
static inline bool radeon_has_atpx(void) { return false; }
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -107,6 +107,13 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
|
|||
flags |= RADEON_IS_PCI;
|
||||
}
|
||||
|
||||
if (radeon_runtime_pm == 1)
|
||||
flags |= RADEON_IS_PX;
|
||||
else if ((radeon_runtime_pm == -1) &&
|
||||
radeon_has_atpx() &&
|
||||
((flags & RADEON_IS_IGP) == 0))
|
||||
flags |= RADEON_IS_PX;
|
||||
|
||||
/* radeon_device_init should report only fatal error
|
||||
* like memory allocation failure or iomapping failure,
|
||||
* or memory manager initialization failure, it must
|
||||
|
@ -137,8 +144,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
|
|||
"Error during ACPI methods call\n");
|
||||
}
|
||||
|
||||
if ((radeon_runtime_pm == 1) ||
|
||||
((radeon_runtime_pm == -1) && radeon_is_px())) {
|
||||
if (radeon_is_px(dev)) {
|
||||
pm_runtime_use_autosuspend(dev->dev);
|
||||
pm_runtime_set_autosuspend_delay(dev->dev, 5000);
|
||||
pm_runtime_set_active(dev->dev);
|
||||
|
@ -568,12 +574,17 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|||
}
|
||||
|
||||
r = radeon_vm_init(rdev, &fpriv->vm);
|
||||
if (r)
|
||||
if (r) {
|
||||
kfree(fpriv);
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
||||
if (r)
|
||||
if (r) {
|
||||
radeon_vm_fini(rdev, &fpriv->vm);
|
||||
kfree(fpriv);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* map the ib pool buffer read only into
|
||||
* virtual address space */
|
||||
|
|
|
@ -57,9 +57,14 @@
|
|||
#define BTC_MC_UCODE_SIZE 6024
|
||||
#define CAYMAN_MC_UCODE_SIZE 6037
|
||||
#define SI_MC_UCODE_SIZE 7769
|
||||
#define TAHITI_MC_UCODE_SIZE 7808
|
||||
#define PITCAIRN_MC_UCODE_SIZE 7775
|
||||
#define VERDE_MC_UCODE_SIZE 7875
|
||||
#define OLAND_MC_UCODE_SIZE 7863
|
||||
#define CIK_MC_UCODE_SIZE 7866
|
||||
#define BONAIRE_MC_UCODE_SIZE 7866
|
||||
#define BONAIRE_MC2_UCODE_SIZE 7948
|
||||
#define HAWAII_MC_UCODE_SIZE 7933
|
||||
#define HAWAII_MC2_UCODE_SIZE 8091
|
||||
|
||||
/* SDMA */
|
||||
#define CIK_SDMA_UCODE_SIZE 1050
|
||||
|
|
|
@ -613,7 +613,7 @@ void radeon_vce_fence_emit(struct radeon_device *rdev,
|
|||
struct radeon_fence *fence)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[fence->ring];
|
||||
uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
|
||||
uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
|
||||
|
||||
radeon_ring_write(ring, VCE_CMD_FENCE);
|
||||
radeon_ring_write(ring, addr);
|
||||
|
|
|
@ -39,30 +39,35 @@ MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
|
|||
MODULE_FIRMWARE("radeon/TAHITI_me.bin");
|
||||
MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
|
||||
MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
|
||||
MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
|
||||
MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_me.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_ce.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_mc.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/VERDE_smc.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_me.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_ce.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_mc.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/OLAND_smc.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_me.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
|
||||
|
||||
|
@ -1467,36 +1472,33 @@ int si_mc_load_microcode(struct radeon_device *rdev)
|
|||
const __be32 *fw_data;
|
||||
u32 running, blackout = 0;
|
||||
u32 *io_mc_regs;
|
||||
int i, ucode_size, regs_size;
|
||||
int i, regs_size, ucode_size;
|
||||
|
||||
if (!rdev->mc_fw)
|
||||
return -EINVAL;
|
||||
|
||||
ucode_size = rdev->mc_fw->size / 4;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_TAHITI:
|
||||
io_mc_regs = (u32 *)&tahiti_io_mc_regs;
|
||||
ucode_size = SI_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
case CHIP_PITCAIRN:
|
||||
io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
|
||||
ucode_size = SI_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
case CHIP_VERDE:
|
||||
default:
|
||||
io_mc_regs = (u32 *)&verde_io_mc_regs;
|
||||
ucode_size = SI_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
case CHIP_OLAND:
|
||||
io_mc_regs = (u32 *)&oland_io_mc_regs;
|
||||
ucode_size = OLAND_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
case CHIP_HAINAN:
|
||||
io_mc_regs = (u32 *)&hainan_io_mc_regs;
|
||||
ucode_size = OLAND_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
}
|
||||
|
@ -1552,7 +1554,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
const char *chip_name;
|
||||
const char *rlc_chip_name;
|
||||
size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
|
||||
size_t smc_req_size;
|
||||
size_t smc_req_size, mc2_req_size;
|
||||
char fw_name[30];
|
||||
int err;
|
||||
|
||||
|
@ -1567,6 +1569,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
ce_req_size = SI_CE_UCODE_SIZE * 4;
|
||||
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
|
||||
mc_req_size = SI_MC_UCODE_SIZE * 4;
|
||||
mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
|
||||
smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
|
||||
break;
|
||||
case CHIP_PITCAIRN:
|
||||
|
@ -1577,6 +1580,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
ce_req_size = SI_CE_UCODE_SIZE * 4;
|
||||
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
|
||||
mc_req_size = SI_MC_UCODE_SIZE * 4;
|
||||
mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
|
||||
smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
|
||||
break;
|
||||
case CHIP_VERDE:
|
||||
|
@ -1587,6 +1591,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
ce_req_size = SI_CE_UCODE_SIZE * 4;
|
||||
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
|
||||
mc_req_size = SI_MC_UCODE_SIZE * 4;
|
||||
mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
|
||||
smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
|
||||
break;
|
||||
case CHIP_OLAND:
|
||||
|
@ -1596,7 +1601,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
me_req_size = SI_PM4_UCODE_SIZE * 4;
|
||||
ce_req_size = SI_CE_UCODE_SIZE * 4;
|
||||
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
|
||||
mc_req_size = OLAND_MC_UCODE_SIZE * 4;
|
||||
mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
|
||||
smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
|
||||
break;
|
||||
case CHIP_HAINAN:
|
||||
|
@ -1606,7 +1611,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
me_req_size = SI_PM4_UCODE_SIZE * 4;
|
||||
ce_req_size = SI_CE_UCODE_SIZE * 4;
|
||||
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
|
||||
mc_req_size = OLAND_MC_UCODE_SIZE * 4;
|
||||
mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
|
||||
smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
|
||||
break;
|
||||
default: BUG();
|
||||
|
@ -1659,16 +1664,22 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
err = -EINVAL;
|
||||
}
|
||||
|
||||
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
|
||||
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
|
||||
err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
|
||||
if (err)
|
||||
goto out;
|
||||
if (rdev->mc_fw->size != mc_req_size) {
|
||||
if (err) {
|
||||
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
|
||||
err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
|
||||
if (err)
|
||||
goto out;
|
||||
}
|
||||
if ((rdev->mc_fw->size != mc_req_size) &&
|
||||
(rdev->mc_fw->size != mc2_req_size)) {
|
||||
printk(KERN_ERR
|
||||
"si_mc: Bogus length %zu in firmware \"%s\"\n",
|
||||
rdev->mc_fw->size, fw_name);
|
||||
err = -EINVAL;
|
||||
}
|
||||
DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
|
||||
|
||||
snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
|
||||
err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
|
||||
|
|
Загрузка…
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