ARM: 64-bit DT updates for v4.6
The arm64 device tree changes make up an increasing portion of the overall changes, so they are kept separate from the 32-bit devicetree changes and from the other arm64 updates. Newly added SoCs and boards are: - 96Boards Husky board - AMD Overdrive board - Amlogic S905 SoC and related Tronsmart boxes - Annapurna Labs Alpine family and development board - Broadcom Vulcan servers - Broadcom Northstar 2 SoC - Marvell Armada 3700 family and development board - Qualcomm MSM8996 SoC Additional devices are enabled for existing platforms from Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a couple of other updates for Rockchip, Xilinx and NXP/Freescale. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIUAwUAVu67Q2CrR//JCVInAQL0ng/47UBpXwVw1V5zm9lUIA1oluo/cKgFyGsi G8wOzoMwmZocDKXC7mONS6c6AjeqszTNQ8V2j2ieU7G7S+moi8SnTcc8pJKD26HL KvsxGtnfKXFAfZkJ8iERxHmZojHN93EF01P3R+pEIlKzFs+8Mx66VbUp2mVEMrHR wClzoW1n49kdpQhGuGeryFufAgUd/OKG2VDosCDR5hpoTNYWenuIQB5VHtiow08U 9SVEBUW6YxDV3hiyt4Vd5FvrPT/PJEPchmnscgC8L/sVD57XeH5h68GE4mDplc68 QxzFqDAHuInPS/p6h9zFALawh8lXvu+ERTt6XZqGxzvhEkifx6grOBVCaVSbfpct JLzFUZKcGXDLekVq0GQWj7ZCQnWeRSdtIGBtoaEzLzjZ0aGeSeN0nuldWFRx3Eml 3eTpHsyLOtjsSjZcdSWtzSBbN2OuymvSKfjdHfqANbpsUYZREI/HXNg/WLCzhsbr o7VQig/dkSQ+Od39omKk1AP5adLpCdUc0nm2omdUJRVEuJ0l9fLp3Td4nZTtOPle Vbf5lYHGAMCrgzPEJnMxtUb1XlstQdij2FEYTeqUqHyZ1kZNaGOaWWgXNW6ORyn9 eOav61eWwZ0qvppaQKzv7rIV5qtP5Zg3kLvsNvQpWhr3ev14n0rvFu1RAy/yz2gR zMtRVagq/w== =izw3 -----END PGP SIGNATURE----- Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "The arm64 device tree changes make up an increasing portion of the overall changes, so they are kept separate from the 32-bit devicetree changes and from the other arm64 updates. Newly added SoCs and boards are: - 96Boards Husky board - AMD Overdrive board - Amlogic S905 SoC and related Tronsmart boxes - Annapurna Labs Alpine family and development board - Broadcom Vulcan servers - Broadcom Northstar 2 SoC - Marvell Armada 3700 family and development board - Qualcomm MSM8996 SoC Additional devices are enabled for existing platforms from Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a couple of other updates for Rockchip, Xilinx and NXP/Freescale" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits) ARM64: dts: amlogic: Add Tronsmart Vega S95 configs Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards ARM64: dts: Prepare configs for Amlogic Meson GXBaby Documentation: devicetree: amlogic: Document Meson GXBaby devicetree: bindings: Add vendor prefix for Tronsmart arm64: dts: qcom: Fix MPP's function used for LED control arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi arm64: dts: add the Alpine v2 EVP arm64: dts: marvell: re-order Device Tree nodes for Armada AP806 arm64: dts: marvell: update Armada AP806 clock description arm64: dts: marvell: add Device Tree files for Armada 7K/8K arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform. arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver arm64: dts: apm: mailbox device tree node for APM X-Gene platform. arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2 arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2 ...
This commit is contained in:
Linus Torvalds
Коммит
915c56bc01
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@ -13,8 +13,15 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
|
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Required root node property:
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compatible: "amlogic,meson8b";
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Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
|
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Required root node property:
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compatible: "amlogic,meson-gxbb";
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Board compatible values:
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- "geniatech,atv1200" (Meson6)
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- "minix,neo-x8" (Meson8)
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- "tronfy,mxq" (Meson8b)
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- "hardkernel,odroid-c1" (Meson8b)
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- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
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|
|
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@ -0,0 +1,10 @@
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Broadcom Vulcan device tree bindings
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------------------------------------
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Boards with Broadcom Vulcan shall have the following root property:
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Broadcom Vulcan Evaluation Board:
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compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
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Generic Vulcan board:
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compatible = "brcm,vulcan-soc";
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@ -167,6 +167,7 @@ nodes to be present and contain the properties described below.
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"brcm,vulcan"
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"cavium,thunder"
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"faraday,fa526"
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"intel,sa110"
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|
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@ -0,0 +1,16 @@
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Marvell Armada 37xx Platforms Device Tree Bindings
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--------------------------------------------------
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Boards using a SoC of the Marvell Armada 37xx family must carry the
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following root node property:
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- compatible: must contain "marvell,armada3710"
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In addition, boards using the Marvell Armada 3720 SoC shall have the
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following property before the previous one:
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- compatible: must contain "marvell,armada3720"
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Example:
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compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
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@ -0,0 +1,24 @@
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Marvell Armada 7K/8K Platforms Device Tree Bindings
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---------------------------------------------------
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Boards using a SoC of the Marvell Armada 7K or 8K families must carry
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the following root node property:
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- compatible, with one of the following values:
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- "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
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when the SoC being used is the Armada 7020
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- "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
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when the SoC being used is the Armada 7040
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- "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
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when the SoC being used is the Armada 8020
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- "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
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when the SoC being used is the Armada 8040
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Example:
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compatible = "marvell,armada7040-db", "marvell,armada7040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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@ -14,6 +14,7 @@ Required properties:
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- "cavium,octeon-7130-ahci"
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- "ibm,476gtr-ahci"
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- "marvell,armada-380-ahci"
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- "marvell,armada-3700-ahci"
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- "snps,dwc-ahci"
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- "snps,exynos5440-ahci"
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- "snps,spear-ahci"
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@ -246,6 +246,7 @@ toshiba Toshiba Corporation
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toumaz Toumaz
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tplink TP-LINK Technologies Co., Ltd.
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tronfy Tronfy
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tronsmart Tronsmart
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truly Truly Semiconductors Limited
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upisemi uPI Semiconductor Corp.
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urt United Radiant Technology Corporation
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|
|
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@ -0,0 +1,17 @@
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ARM AMBA Primecell SP805 Watchdog
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Required properties:
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- compatible: Should be "arm,sp805" & "arm,primecell"
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- reg: Should contain location and length for watchdog timer register.
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- interrupts: Should contain the list of watchdog timer interrupts.
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- clocks: clocks driving the watchdog timer hardware. This list should be 2
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clocks. With 2 clocks, the order is wdogclk clock, apb_pclk.
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Example:
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watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x66090000 0x1000>;
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_pclk>,<&apb_pclk>;
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clock-names = "wdogclk", "apb_pclk";
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};
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@ -679,11 +679,19 @@ F: drivers/gpu/drm/radeon/radeon_kfd.c
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F: drivers/gpu/drm/radeon/radeon_kfd.h
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F: include/uapi/linux/kfd_ioctl.h
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AMD SEATTLE DEVICE TREE SUPPORT
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M: Brijesh Singh <brijeshkumar.singh@amd.com>
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M: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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M: Tom Lendacky <thomas.lendacky@amd.com>
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S: Supported
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F: arch/arm64/boot/dts/amd/
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AMD XGBE DRIVER
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M: Tom Lendacky <thomas.lendacky@amd.com>
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L: netdev@vger.kernel.org
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S: Supported
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F: drivers/net/ethernet/amd/xgbe/
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F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
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AMS (Apple Motion Sensor) DRIVER
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M: Michael Hanselmann <linux-kernel@hansmi.ch>
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|
|
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@ -1,5 +1,7 @@
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dts-dirs += al
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dts-dirs += altera
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dts-dirs += amd
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dts-dirs += amlogic
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dts-dirs += apm
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dts-dirs += arm
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dts-dirs += broadcom
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@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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@ -0,0 +1,53 @@
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/*
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* Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Antoine Tenart <antoine.tenart@free-electrons.com>
|
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*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
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||||
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#include "alpine-v2.dtsi"
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/ {
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model = "Annapurna Labs Alpine v2 EVP";
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compatible = "al,alpine-v2-evp", "al,alpine-v2";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 { status = "okay"; };
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@ -0,0 +1,236 @@
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/*
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* Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Antoine Tenart <antoine.tenart@free-electrons.com>
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
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* BSD license below:
|
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*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
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* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Annapurna Labs Alpine v2";
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compatible = "al,alpine-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
|
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enable-method = "psci";
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};
|
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
|
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method = "smc";
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||||
cpu_suspend = <0x84000001>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0x84000003>;
|
||||
};
|
||||
|
||||
sbclk: sbclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gic: gic@f0100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
|
||||
<0x0 0xf0280000 0x0 0x200000>, /* GICR */
|
||||
<0x0 0xf0100000 0x0 0x2000>, /* GICC */
|
||||
<0x0 0xf0110000 0x0 0x2000>, /* GICV */
|
||||
<0x0 0xf0120000 0x0 0x2000>; /* GICH */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
pci@fbc00000 {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x0 0xfbc00000 0x0 0x100000>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
/* add legacy interrupts for SATA only */
|
||||
interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
|
||||
<0x4800 0 0 1 &gic 0 54 4>;
|
||||
/* 32 bit non prefetchable memory space */
|
||||
ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
|
||||
bus-range = <0x00 0x00>;
|
||||
msi-parent = <&msix>;
|
||||
};
|
||||
|
||||
msix: msix@fbe00000 {
|
||||
compatible = "al,alpine-msix";
|
||||
reg = <0x0 0xfbe00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
al,msi-base-spi = <160>;
|
||||
al,msi-num-spis = <160>;
|
||||
};
|
||||
|
||||
io-fabric {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0xfc000000 0x2000000>;
|
||||
|
||||
uart0: serial@1883000 {
|
||||
compatible = "ns16550a";
|
||||
device_type = "serial";
|
||||
reg = <0x1883000 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <500000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@1884000 {
|
||||
compatible = "ns16550a";
|
||||
device_type = "serial";
|
||||
reg = <0x1884000 0x1000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <500000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@1885000 {
|
||||
compatible = "ns16550a";
|
||||
device_type = "serial";
|
||||
reg = <0x1885000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <500000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@1886000 {
|
||||
compatible = "ns16550a";
|
||||
device_type = "serial";
|
||||
reg = <0x1886000 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <500000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer0: timer@1890000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x1890000 0x1000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sbclk>;
|
||||
};
|
||||
|
||||
timer1: timer@1891000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x1891000 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sbclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer2: timer@1892000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x1892000 0x1000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sbclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer3: timer@1893000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x1893000 0x1000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sbclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,4 +1,6 @@
|
|||
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb
|
||||
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
|
||||
amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \
|
||||
husky.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* DTS file for AMD Seattle Overdrive Development Board
|
||||
* Note: For Seattle Rev.B0
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "amd-seattle-soc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
|
||||
compatible = "amd,seattle-overdrive", "amd,seattle";
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
&ccp0 {
|
||||
status = "ok";
|
||||
amd,zlib-support = <1>;
|
||||
};
|
||||
|
||||
/**
|
||||
* NOTE: In Rev.B, gpio0 is reserved.
|
||||
*/
|
||||
&gpio1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "ok";
|
||||
sdcard0: sdcard@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3200 3400>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,com-mode = <0x0>;
|
||||
pl022,rx-level-trig = <0>;
|
||||
pl022,tx-level-trig = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ipmi_kcs {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&smb0 {
|
||||
/include/ "amd-seattle-xgbe-b.dtsi"
|
||||
};
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* DTS file for AMD Seattle Overdrive Development Board
|
||||
* Note: For Seattle Rev.B1
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "amd-seattle-soc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";
|
||||
compatible = "amd,seattle-overdrive", "amd,seattle";
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
&ccp0 {
|
||||
status = "ok";
|
||||
amd,zlib-support = <1>;
|
||||
};
|
||||
|
||||
/**
|
||||
* NOTE: In Rev.B, gpio0 is reserved.
|
||||
*/
|
||||
&gpio1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "ok";
|
||||
sdcard0: sdcard@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3200 3400>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,com-mode = <0x0>;
|
||||
pl022,rx-level-trig = <0>;
|
||||
pl022,tx-level-trig = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ipmi_kcs {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&smb0 {
|
||||
/include/ "amd-seattle-xgbe-b.dtsi"
|
||||
};
|
||||
|
|
@ -18,8 +18,8 @@
|
|||
#size-cells = <2>;
|
||||
reg = <0x0 0xe1110000 0 0x1000>,
|
||||
<0x0 0xe112f000 0 0x2000>,
|
||||
<0x0 0xe1140000 0 0x10000>,
|
||||
<0x0 0xe1160000 0 0x10000>;
|
||||
<0x0 0xe1140000 0 0x2000>,
|
||||
<0x0 0xe1160000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
ranges = <0 0 0 0xe1100000 0 0x100000>;
|
||||
v2m0: v2m@e0080000 {
|
||||
|
|
@ -55,25 +55,47 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* DDR range is 40-bit addressing */
|
||||
dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
|
||||
/*
|
||||
* dma-ranges is 40-bit address space containing:
|
||||
* - GICv2m MSI register is at 0xe0080000
|
||||
* - DRAM range [0x8000000000 to 0xffffffffff]
|
||||
*/
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
|
||||
|
||||
/include/ "amd-seattle-clks.dtsi"
|
||||
|
||||
sata0: sata@e0300000 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0 0xe0300000 0 0x800>;
|
||||
reg = <0 0xe0300000 0 0xf0000>;
|
||||
interrupts = <0 355 4>;
|
||||
clocks = <&sataclk_333mhz>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
/* This is for Rev B only */
|
||||
sata1: sata@e0d00000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0 0xe0d00000 0 0xf0000>;
|
||||
interrupts = <0 354 4>;
|
||||
clocks = <&sataclk_333mhz>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
i2c0: i2c@e1000000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0xe1000000 0 0x1000>;
|
||||
interrupts = <0 357 4>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
};
|
||||
|
||||
i2c1: i2c@e0050000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0xe0050000 0 0x1000>;
|
||||
interrupts = <0 340 4>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
};
|
||||
|
||||
serial0: serial@e1010000 {
|
||||
|
|
@ -87,7 +109,6 @@
|
|||
spi0: ssp@e1020000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1020000 0 0x1000>;
|
||||
spi-controller;
|
||||
interrupts = <0 330 4>;
|
||||
|
|
@ -98,7 +119,6 @@
|
|||
spi1: ssp@e1030000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1030000 0 0x1000>;
|
||||
spi-controller;
|
||||
interrupts = <0 329 4>;
|
||||
|
|
@ -109,7 +129,7 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e1040000 {
|
||||
gpio0: gpio@e1040000 { /* Not available to OS for B0 */
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -118,18 +138,59 @@
|
|||
interrupts = <0 359 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio1: gpio@e1050000 {
|
||||
gpio1: gpio@e1050000 { /* [0:7] */
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1050000 0 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 358 4>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio2: gpio@e0020000 { /* [8:15] */
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe0020000 0 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 366 4>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio3: gpio@e0030000 { /* [16:23] */
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe0030000 0 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 365 4>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio4: gpio@e0080000 { /* [24] */
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe0080000 0 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 361 4>;
|
||||
clocks = <&miscclk_250mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
|
|
@ -159,7 +220,7 @@
|
|||
<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
|
||||
|
||||
dma-coherent;
|
||||
dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
|
||||
dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
|
||||
ranges =
|
||||
/* I/O Memory (size=64K) */
|
||||
<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
|
||||
|
|
@ -168,5 +229,22 @@
|
|||
/* 64-bit MMIO (size= 124G) */
|
||||
<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
|
||||
};
|
||||
|
||||
/* Perf CCN504 PMU */
|
||||
ccn: ccn@e8000000 {
|
||||
compatible = "arm,ccn-504";
|
||||
reg = <0x0 0xe8000000 0 0x1000000>;
|
||||
interrupts = <0 380 4>;
|
||||
};
|
||||
|
||||
ipmi_kcs: kcs@e0010000 {
|
||||
status = "disabled";
|
||||
compatible = "ipmi-kcs";
|
||||
device_type = "ipmi";
|
||||
reg = <0x0 0xe0010000 0 0x8>;
|
||||
interrupts = <0 389 4>;
|
||||
reg-size = <1>;
|
||||
reg-spacing = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* DTS file for AMD Seattle XGBE (RevB)
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
xgmacclk0_dma_250mhz: clk250mhz_0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
clock-output-names = "xgmacclk0_dma_250mhz";
|
||||
};
|
||||
|
||||
xgmacclk0_ptp_250mhz: clk250mhz_1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
clock-output-names = "xgmacclk0_ptp_250mhz";
|
||||
};
|
||||
|
||||
xgmacclk1_dma_250mhz: clk250mhz_2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
clock-output-names = "xgmacclk1_dma_250mhz";
|
||||
};
|
||||
|
||||
xgmacclk1_ptp_250mhz: clk250mhz_3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
clock-output-names = "xgmacclk1_ptp_250mhz";
|
||||
};
|
||||
|
||||
xgmac0: xgmac@e0700000 {
|
||||
compatible = "amd,xgbe-seattle-v1a";
|
||||
reg = <0 0xe0700000 0 0x80000>,
|
||||
<0 0xe0780000 0 0x80000>,
|
||||
<0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
|
||||
<0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
|
||||
<0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
|
||||
interrupts = <0 325 4>,
|
||||
<0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
|
||||
<0 323 4>;
|
||||
amd,per-channel-interrupt;
|
||||
amd,speed-set = <0>;
|
||||
amd,serdes-blwc = <1>, <1>, <0>;
|
||||
amd,serdes-cdr-rate = <2>, <2>, <7>;
|
||||
amd,serdes-pq-skew = <10>, <10>, <18>;
|
||||
amd,serdes-tx-amp = <0>, <0>, <0>;
|
||||
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
|
||||
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
|
||||
mac-address = [ 02 A1 A2 A3 A4 A5 ];
|
||||
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
|
||||
clock-names = "dma_clk", "ptp_clk";
|
||||
phy-mode = "xgmii";
|
||||
#stream-id-cells = <16>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xgmac1: xgmac@e0900000 {
|
||||
compatible = "amd,xgbe-seattle-v1a";
|
||||
reg = <0 0xe0900000 0 0x80000>,
|
||||
<0 0xe0980000 0 0x80000>,
|
||||
<0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
|
||||
<0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
|
||||
<0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
|
||||
interrupts = <0 324 4>,
|
||||
<0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
|
||||
<0 322 4>;
|
||||
amd,per-channel-interrupt;
|
||||
amd,speed-set = <0>;
|
||||
amd,serdes-blwc = <1>, <1>, <0>;
|
||||
amd,serdes-cdr-rate = <2>, <2>, <7>;
|
||||
amd,serdes-pq-skew = <10>, <10>, <18>;
|
||||
amd,serdes-tx-amp = <0>, <0>, <0>;
|
||||
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
|
||||
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
|
||||
mac-address = [ 02 B1 B2 B3 B4 B5 ];
|
||||
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
|
||||
clock-names = "dma_clk", "ptp_clk";
|
||||
phy-mode = "xgmii";
|
||||
#stream-id-cells = <16>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xgmac0_smmu: smmu@e0600000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0600000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = /* Uses combined intr for both
|
||||
* global and context
|
||||
*/
|
||||
<0 336 4>,
|
||||
<0 336 4>;
|
||||
|
||||
mmu-masters = <&xgmac0
|
||||
0 1 2 3 4 5 6 7
|
||||
16 17 18 19 20 21 22 23
|
||||
>;
|
||||
};
|
||||
|
||||
xgmac1_smmu: smmu@e0800000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0800000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = /* Uses combined intr for both
|
||||
* global and context
|
||||
*/
|
||||
<0 335 4>,
|
||||
<0 335 4>;
|
||||
|
||||
mmu-masters = <&xgmac1
|
||||
0 1 2 3 4 5 6 7
|
||||
16 17 18 19 20 21 22 23
|
||||
>;
|
||||
};
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board
|
||||
* Note: Based-on AMD Seattle Rev.B0
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "amd-seattle-soc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Linaro 96Boards Enterprise Edition Server (Husky) Board";
|
||||
compatible = "amd,seattle-overdrive", "amd,seattle";
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
&ccp0 {
|
||||
status = "ok";
|
||||
amd,zlib-support = <1>;
|
||||
};
|
||||
|
||||
/**
|
||||
* NOTE: In Rev.B, gpio0 is reserved.
|
||||
*/
|
||||
&gpio1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "ok";
|
||||
sdcard0: sdcard@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3200 3400>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,com-mode = <0x0>;
|
||||
pl022,rx-level-trig = <0>;
|
||||
pl022,tx-level-trig = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&smb0 {
|
||||
/include/ "amd-seattle-xgbe-b.dtsi"
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-vega-s95.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "tronsmart,vega-s95-meta", "tronsmart,vega-s95", "amlogic,meson-gxbb";
|
||||
model = "Tronsmart Vega S95 Meta";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-vega-s95.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "tronsmart,vega-s95-pro", "tronsmart,vega-s95", "amlogic,meson-gxbb";
|
||||
model = "Tronsmart Vega S95 Pro";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-vega-s95.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "tronsmart,vega-s95-telos", "tronsmart,vega-s95", "amlogic,meson-gxbb";
|
||||
model = "Tronsmart Vega S95 Telos";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "meson-gxbb.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,meson-gxbb";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
serial1 = &uart_A;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
|
||||
};
|
||||
|
||||
xtal: xtal-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xtal";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cbus: cbus@c1100000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc1100000 0x0 0x100000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
|
||||
|
||||
uart_A: serial@84c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0x0 0x084c0 0x0 0x14>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@c4301000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x0 0xc4301000 0 0x1000>,
|
||||
<0x0 0xc4302000 0 0x2000>,
|
||||
<0x0 0xc4304000 0 0x2000>,
|
||||
<0x0 0xc4306000 0 0x2000>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
};
|
||||
|
||||
aobus: aobus@c8100000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8100000 0x0 0x100000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
|
||||
|
||||
uart_AO: serial@4c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0x0 0x004c0 0x0 0x14>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
apb: apb@d0000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xd0000000 0x0 0x200000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -30,7 +30,8 @@
|
|||
label = "POWER";
|
||||
linux,code = <116>;
|
||||
linux,input-type = <0x1>;
|
||||
interrupts = <0x0 0x28 0x1>;
|
||||
interrupt-parent = <&sbgpio>;
|
||||
interrupts = <0x0 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,8 @@
|
|||
label = "POWER";
|
||||
linux,code = <116>;
|
||||
linux,input-type = <0x1>;
|
||||
interrupts = <0x0 0x2d 0x1>;
|
||||
interrupt-parent = <&sbgpio>;
|
||||
interrupts = <0x5 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@
|
|||
};
|
||||
|
||||
socpll: socpll@17000120 {
|
||||
compatible = "apm,xgene-socpll-clock";
|
||||
compatible = "apm,xgene-socpll-v2-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&refclk 0>;
|
||||
reg = <0x0 0x17000120 0x0 0x1000>;
|
||||
|
|
@ -453,6 +453,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
mailbox: mailbox@10540000 {
|
||||
compatible = "apm,xgene-slimpro-mbox";
|
||||
reg = <0x0 0x10540000 0x0 0x8000>;
|
||||
#mbox-cells = <1>;
|
||||
interrupts = <0x0 0x0 0x4
|
||||
0x0 0x1 0x4
|
||||
0x0 0x2 0x4
|
||||
0x0 0x3 0x4
|
||||
0x0 0x4 0x4
|
||||
0x0 0x5 0x4
|
||||
0x0 0x6 0x4
|
||||
0x0 0x7 0x4>;
|
||||
};
|
||||
|
||||
i2cslimpro {
|
||||
compatible = "apm,xgene-slimpro-i2c";
|
||||
mboxes = <&mailbox 0>;
|
||||
};
|
||||
|
||||
serial0: serial@10600000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
|
|
@ -598,6 +617,12 @@
|
|||
<0x0 0x2d 0x1>,
|
||||
<0x0 0x2e 0x1>,
|
||||
<0x0 0x2f 0x1>;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
apm,nr-gpios = <22>;
|
||||
apm,nr-irqs = <8>;
|
||||
apm,irq-start = <8>;
|
||||
};
|
||||
|
||||
sgenet0: ethernet@1f610000 {
|
||||
|
|
|
|||
|
|
@ -697,6 +697,25 @@
|
|||
msi-parent = <&msi>;
|
||||
};
|
||||
|
||||
mailbox: mailbox@10540000 {
|
||||
compatible = "apm,xgene-slimpro-mbox";
|
||||
reg = <0x0 0x10540000 0x0 0xa000>;
|
||||
#mbox-cells = <1>;
|
||||
interrupts = <0x0 0x0 0x4>,
|
||||
<0x0 0x1 0x4>,
|
||||
<0x0 0x2 0x4>,
|
||||
<0x0 0x3 0x4>,
|
||||
<0x0 0x4 0x4>,
|
||||
<0x0 0x5 0x4>,
|
||||
<0x0 0x6 0x4>,
|
||||
<0x0 0x7 0x4>;
|
||||
};
|
||||
|
||||
i2cslimpro {
|
||||
compatible = "apm,xgene-slimpro-i2c";
|
||||
mboxes = <&mailbox 0>;
|
||||
};
|
||||
|
||||
serial0: serial@1c020000 {
|
||||
status = "disabled";
|
||||
device_type = "serial";
|
||||
|
|
@ -889,6 +908,9 @@
|
|||
<0x0 0x2b 0x1>,
|
||||
<0x0 0x2c 0x1>,
|
||||
<0x0 0x2d 0x1>;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
rtc: rtc@10510000 {
|
||||
|
|
|
|||
|
|
@ -52,6 +52,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
|
@ -64,6 +72,10 @@
|
|||
status = "ok";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&nand {
|
||||
nandcs@0 {
|
||||
compatible = "brcm,nandcs";
|
||||
|
|
|
|||
|
|
@ -137,6 +137,80 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@20020000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0 0x20020000 0 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
|
||||
|
||||
brcm,pcie-ob;
|
||||
brcm,pcie-ob-oarr-size;
|
||||
brcm,pcie-ob-axi-offset = <0x00000000>;
|
||||
brcm,pcie-ob-window-size = <256>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
msi-parent = <&msi0>;
|
||||
msi0: msi@20020000 {
|
||||
compatible = "brcm,iproc-msi";
|
||||
msi-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 278 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 279 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 280 IRQ_TYPE_NONE>;
|
||||
brcm,num-eq-region = <1>;
|
||||
brcm,num-msi-msg-region = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie4: pcie@50020000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0 0x50020000 0 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <4>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
|
||||
|
||||
brcm,pcie-ob;
|
||||
brcm,pcie-ob-oarr-size;
|
||||
brcm,pcie-ob-axi-offset = <0x30000000>;
|
||||
brcm,pcie-ob-window-size = <256>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
msi-parent = <&msi4>;
|
||||
msi4: msi@50020000 {
|
||||
compatible = "brcm,iproc-msi";
|
||||
msi-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 302 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 303 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 304 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -256,6 +330,46 @@
|
|||
<0x65260000 0x1000>;
|
||||
};
|
||||
|
||||
timer0: timer@66030000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x66030000 0x1000>;
|
||||
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>,
|
||||
<&iprocslow>,
|
||||
<&iprocslow>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
timer1: timer@66040000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x66040000 0x1000>;
|
||||
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>,
|
||||
<&iprocslow>,
|
||||
<&iprocslow>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
timer2: timer@66050000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x66050000 0x1000>;
|
||||
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>,
|
||||
<&iprocslow>,
|
||||
<&iprocslow>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
timer3: timer@66060000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x66060000 0x1000>;
|
||||
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>,
|
||||
<&iprocslow>,
|
||||
<&iprocslow>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
i2c0: i2c@66080000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x66080000 0x100>;
|
||||
|
|
@ -266,6 +380,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt0: watchdog@66090000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x66090000 0x1000>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>, <&iprocslow>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
i2c1: i2c@660b0000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x660b0000 0x100>;
|
||||
|
|
@ -291,6 +413,24 @@
|
|||
reg = <0x66220000 0x28>;
|
||||
};
|
||||
|
||||
sdio0: sdhci@66420000 {
|
||||
compatible = "brcm,sdhci-iproc-cygnus";
|
||||
reg = <0x66420000 0x100>;
|
||||
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-width = <8>;
|
||||
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: sdhci@66430000 {
|
||||
compatible = "brcm,sdhci-iproc-cygnus";
|
||||
reg = <0x66430000 0x100>;
|
||||
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-width = <8>;
|
||||
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand@66460000 {
|
||||
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
|
||||
reg = <0x66460000 0x600>,
|
||||
|
|
|
|||
|
|
@ -407,6 +407,7 @@
|
|||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <0 60 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
usb1: usb3@3000000 {
|
||||
|
|
@ -414,6 +415,7 @@
|
|||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <0 61 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
usb2: usb3@3100000 {
|
||||
|
|
@ -421,6 +423,7 @@
|
|||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 63 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
|
|
|
|||
|
|
@ -573,6 +573,7 @@
|
|||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 80 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
usb1: usb3@3110000 {
|
||||
|
|
@ -581,6 +582,7 @@
|
|||
reg = <0x0 0x3110000 0x0 0x10000>;
|
||||
interrupts = <0 81 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
ccn@4000000 {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "hip05.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -29,8 +30,25 @@
|
|||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pwrbutton {
|
||||
label = "Power Button";
|
||||
gpios = <&porta 8 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <116>;
|
||||
debounce-interval = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&peri_gpio0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -90,6 +90,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20000>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@20001 {
|
||||
|
|
@ -97,6 +98,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20001>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@20002 {
|
||||
|
|
@ -104,6 +106,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20002>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@20003 {
|
||||
|
|
@ -111,6 +114,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20003>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu4: cpu@20100 {
|
||||
|
|
@ -118,6 +122,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu5: cpu@20101 {
|
||||
|
|
@ -125,6 +130,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20101>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu6: cpu@20102 {
|
||||
|
|
@ -132,6 +138,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20102>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu7: cpu@20103 {
|
||||
|
|
@ -139,6 +146,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20103>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu8: cpu@20200 {
|
||||
|
|
@ -146,6 +154,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu9: cpu@20201 {
|
||||
|
|
@ -153,6 +162,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20201>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu10: cpu@20202 {
|
||||
|
|
@ -160,6 +170,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20202>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu11: cpu@20203 {
|
||||
|
|
@ -167,6 +178,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20203>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu12: cpu@20300 {
|
||||
|
|
@ -174,6 +186,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu13: cpu@20301 {
|
||||
|
|
@ -181,6 +194,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20301>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu14: cpu@20302 {
|
||||
|
|
@ -188,6 +202,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20302>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu15: cpu@20303 {
|
||||
|
|
@ -195,6 +210,23 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x20303>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cluster0_l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
cluster1_l2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
cluster2_l2: l2-cache2 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
cluster3_l2: l2-cache3 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -214,11 +246,29 @@
|
|||
<0x0 0xfe020000 0 0x10000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its_totems: interrupt-controller@8c000000 {
|
||||
its_peri: interrupt-controller@8c000000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0x8c000000 0x0 0x40000>;
|
||||
};
|
||||
|
||||
its_m3: interrupt-controller@a3000000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0xa3000000 0x0 0x40000>;
|
||||
};
|
||||
|
||||
its_pcie: interrupt-controller@b7000000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0xb7000000 0x0 0x40000>;
|
||||
};
|
||||
|
||||
its_dsa: interrupt-controller@c6000000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0xc6000000 0x0 0x40000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
@ -230,7 +280,7 @@
|
|||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -272,5 +322,43 @@
|
|||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
peri_gpio0: gpio@802e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x802e0000 0x0 0x10000>;
|
||||
status = "disabled";
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
peri_gpio1: gpio@802f0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x802f0000 0x0 0x10000>;
|
||||
status = "disabled";
|
||||
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,11 @@
|
|||
# Berlin SoC Family
|
||||
dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
|
||||
dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
|
||||
|
||||
# Mvebu SoC Family
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 371x family of SoCs
|
||||
* (also named 88F3710)
|
||||
*
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-37xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 3710 SoC";
|
||||
compatible = "marvell,armada3710", "marvell,armada3700";
|
||||
};
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada 3720 development board
|
||||
* (DB-88F3720-DDR3)
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "armada-372x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
|
||||
compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
/*
|
||||
* Exported on the micro USB connector CON32
|
||||
* through an FTDI
|
||||
*/
|
||||
uart0: serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON31 */
|
||||
usb3@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON3 */
|
||||
sata@e0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 372x family of SoCs
|
||||
* (also named 88F3720)
|
||||
*
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-37xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 3720 SoC";
|
||||
compatible = "marvell,armada3720", "marvell,armada3710";
|
||||
|
||||
cpus {
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 37xx family of SoCs.
|
||||
*
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 37xx SoC";
|
||||
compatible = "marvell,armada3700";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
internal-regs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
/* 32M internal register @ 0xd000_0000 */
|
||||
ranges = <0x0 0x0 0xd0000000 0x2000000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "marvell,armada-3700-uart";
|
||||
reg = <0x12000 0x400>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@58000 {
|
||||
compatible = "generic-xhci";
|
||||
reg = <0x58000 0x4000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-3700-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1d00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x1d00000 0x10000>, /* GICD */
|
||||
<0x1d40000 0x40000>; /* GICR */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
|
||||
* one CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-dual.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 7020";
|
||||
compatible = "marvell,armada7020", "marvell,armada-ap806-dual",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 7040 Development board platform
|
||||
*/
|
||||
|
||||
#include "armada-7040.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 7040 DB board";
|
||||
compatible = "marvell,armada7040-db", "marvell,armada7040",
|
||||
"marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ap806 {
|
||||
config-space {
|
||||
spi@510600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x200000 0xce0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@511000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial@512000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
|
||||
* one CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-quad.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 7040";
|
||||
compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
|
||||
* two CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-dual.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 8020";
|
||||
compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
|
||||
* two CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-quad.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 8040";
|
||||
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for Marvell Armada AP806.
|
||||
*/
|
||||
|
||||
#include "armada-ap806.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP806 Dual";
|
||||
compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
cpu@001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for Marvell Armada AP806.
|
||||
*/
|
||||
|
||||
#include "armada-ap806.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP806 Quad";
|
||||
compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
cpu@001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for Marvell Armada AP806.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP806";
|
||||
compatible = "marvell,armada-ap806";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
|
||||
ap806 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
config-space {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x0 0xf0000000 0x1000000>;
|
||||
|
||||
gic: interrupt-controller@210000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x210000 0x10000>,
|
||||
<0x220000 0x20000>,
|
||||
<0x240000 0x20000>,
|
||||
<0x260000 0x20000>;
|
||||
|
||||
gic_v2m0: v2m@280000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x280000 0x1000>;
|
||||
arm,msi-base-spi = <160>;
|
||||
arm,msi-num-spis = <32>;
|
||||
};
|
||||
gic_v2m1: v2m@290000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x290000 0x1000>;
|
||||
arm,msi-base-spi = <192>;
|
||||
arm,msi-num-spis = <32>;
|
||||
};
|
||||
gic_v2m2: v2m@2a0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x2a0000 0x1000>;
|
||||
arm,msi-base-spi = <224>;
|
||||
arm,msi-num-spis = <32>;
|
||||
};
|
||||
gic_v2m3: v2m@2b0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x2b0000 0x1000>;
|
||||
arm,msi-base-spi = <256>;
|
||||
arm,msi-num-spis = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
||||
};
|
||||
|
||||
odmi: odmi@300000 {
|
||||
compatible = "marvell,odmi-controller";
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
marvell,odmi-frames = <4>;
|
||||
reg = <0x300000 0x4000>,
|
||||
<0x304000 0x4000>,
|
||||
<0x308000 0x4000>,
|
||||
<0x30C000 0x4000>;
|
||||
marvell,spi-base = <128>, <136>, <144>, <152>;
|
||||
};
|
||||
|
||||
xor0@400000 {
|
||||
compatible = "marvell,mv-xor-v2";
|
||||
reg = <0x400000 0x1000>,
|
||||
<0x410000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xor1@420000 {
|
||||
compatible = "marvell,mv-xor-v2";
|
||||
reg = <0x420000 0x1000>,
|
||||
<0x430000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xor2@440000 {
|
||||
compatible = "marvell,mv-xor-v2";
|
||||
reg = <0x440000 0x1000>,
|
||||
<0x450000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xor3@460000 {
|
||||
compatible = "marvell,mv-xor-v2";
|
||||
reg = <0x460000 0x1000>,
|
||||
<0x470000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
spi0: spi@510600 {
|
||||
compatible = "marvell,armada-380-spi";
|
||||
reg = <0x510600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ringclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@511000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x511000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&ringclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@512000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x512000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&ringclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@512100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x512100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&ringclk 2>;
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
|
||||
dfx-server@6f8000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x6f8000 0x70000>;
|
||||
|
||||
coreclk: clk@204 {
|
||||
compatible = "marvell,armada-ap806-core-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ddr", "ring", "cpu";
|
||||
};
|
||||
|
||||
ringclk: clk@250 {
|
||||
compatible = "marvell,armada-ap806-ring-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ring-0", "ring-2",
|
||||
"ring-3", "ring-4",
|
||||
"ring-5";
|
||||
clocks = <&coreclk 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
|
@ -214,6 +214,9 @@
|
|||
};
|
||||
|
||||
&pwrap {
|
||||
/* Only MT8173 E1 needs USB power domain */
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
|
||||
|
||||
pmic: mt6397 {
|
||||
compatible = "mediatek,mt6397";
|
||||
interrupt-parent = <&pio>;
|
||||
|
|
|
|||
|
|
@ -277,6 +277,11 @@
|
|||
reg = <0 0x10200620 0 0x20>;
|
||||
};
|
||||
|
||||
efuse: efuse@10206000 {
|
||||
compatible = "mediatek,mt8173-efuse";
|
||||
reg = <0 0x10206000 0 0x1000>;
|
||||
};
|
||||
|
||||
apmixedsys: clock-controller@10209000 {
|
||||
compatible = "mediatek,mt8173-apmixedsys";
|
||||
reg = <0 0x10209000 0 0x1000>;
|
||||
|
|
@ -397,6 +402,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
nor_flash: spi@1100d000 {
|
||||
compatible = "mediatek,mt8173-nor";
|
||||
reg = <0 0x1100d000 0 0xe0>;
|
||||
clocks = <&pericfg CLK_PERI_SPI>,
|
||||
<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
|
||||
clock-names = "spi", "sf";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@11010000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11010000 0 0x70>,
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
pm8916_mpps_leds: pm8916_mpps_leds {
|
||||
pinconf {
|
||||
pins = "mpp2", "mpp3";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
function = "digital";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,4 +10,18 @@
|
|||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
usb_id_default: usb-id-default {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio121";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio121";
|
||||
drive-strength = <8>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
i2c0 = &blsp_i2c2;
|
||||
i2c1 = &blsp_i2c6;
|
||||
i2c3 = &blsp_i2c4;
|
||||
spi0 = &blsp_spi5;
|
||||
spi1 = &blsp_spi3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -127,9 +129,173 @@
|
|||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@07824000 {
|
||||
vmmc-supply = <&pm8916_l8>;
|
||||
vqmmc-supply = <&pm8916_l5>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@78d9000 {
|
||||
extcon = <&usb_id>, <&usb_id>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ehci@78d9000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
phy@78d9000 {
|
||||
v1p8-supply = <&pm8916_l7>;
|
||||
v3p3-supply = <&pm8916_l13>;
|
||||
vddcx-supply = <&pm8916_s1>;
|
||||
extcon = <&usb_id>, <&usb_id>;
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_sw_sel_pm>;
|
||||
};
|
||||
|
||||
lpass@07708000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb2513 {
|
||||
compatible = "smsc,usb3503";
|
||||
reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
|
||||
initial-mode = <1>;
|
||||
};
|
||||
|
||||
usb_id: usb-id {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_id_default>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
&smd_rpm_regulators {
|
||||
vdd_l1_l2_l3-supply = <&pm8916_s3>;
|
||||
vdd_l5-supply = <&pm8916_s3>;
|
||||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
s1 {
|
||||
regulator-min-microvolt = <375000>;
|
||||
regulator-max-microvolt = <1562000>;
|
||||
};
|
||||
|
||||
s3 {
|
||||
regulator-min-microvolt = <375000>;
|
||||
regulator-max-microvolt = <1562000>;
|
||||
};
|
||||
|
||||
s4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l1 {
|
||||
regulator-min-microvolt = <375000>;
|
||||
regulator-max-microvolt = <1525000>;
|
||||
};
|
||||
|
||||
l2 {
|
||||
regulator-min-microvolt = <375000>;
|
||||
regulator-max-microvolt = <1525000>;
|
||||
};
|
||||
|
||||
l3 {
|
||||
regulator-min-microvolt = <375000>;
|
||||
regulator-max-microvolt = <1525000>;
|
||||
};
|
||||
|
||||
l4 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l5 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l6 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l7 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l8 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l9 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l10 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l11 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l12 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l13 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l14 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
/**
|
||||
* 1.8v required on LS expansion
|
||||
* for mezzanine boards
|
||||
*/
|
||||
l15 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
l16 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l17 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
|
||||
l18 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <3337000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@
|
|||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio2";
|
||||
drive-strength = <2>;
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
|
@ -110,13 +110,13 @@
|
|||
pins = "gpio6";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio4", "gpio5", "gpio6", "gpio7";
|
||||
pins = "gpio4", "gpio5", "gpio7";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio6";
|
||||
drive-strength = <2>;
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
|
@ -144,13 +144,13 @@
|
|||
pins = "gpio10";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
pins = "gpio8", "gpio9", "gpio11";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio10";
|
||||
drive-strength = <2>;
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
|
@ -178,13 +178,13 @@
|
|||
pins = "gpio14";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio12", "gpio13", "gpio14", "gpio15";
|
||||
pins = "gpio12", "gpio13", "gpio15";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio14";
|
||||
drive-strength = <2>;
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
|
@ -212,13 +212,13 @@
|
|||
pins = "gpio18";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio16", "gpio17", "gpio18", "gpio19";
|
||||
pins = "gpio16", "gpio17", "gpio19";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio18";
|
||||
drive-strength = <2>;
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
|
@ -246,13 +246,13 @@
|
|||
pins = "gpio22";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio20", "gpio21", "gpio22", "gpio23";
|
||||
pins = "gpio20", "gpio21", "gpio23";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio22";
|
||||
drive-strength = <2>;
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
|
@ -504,4 +504,220 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
ext-codec-lines {
|
||||
ext_codec_lines_act: lines_on {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio67";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio67";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
ext_codec_lines_sus: lines_off {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio67";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio67";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cdc-pdm-lines {
|
||||
cdc_pdm_lines_act: pdm_lines_on {
|
||||
pinmux {
|
||||
function = "cdc_pdm0";
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
drive-strength = <8>;
|
||||
bias-pull-none;
|
||||
};
|
||||
};
|
||||
cdc_pdm_lines_sus: pdm_lines_off {
|
||||
pinmux {
|
||||
function = "cdc_pdm0";
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ext-pri-tlmm-lines {
|
||||
ext_pri_tlmm_lines_act: ext_pa_on {
|
||||
pinmux {
|
||||
function = "pri_mi2s";
|
||||
pins = "gpio113", "gpio114", "gpio115",
|
||||
"gpio116";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio113", "gpio114", "gpio115",
|
||||
"gpio116";
|
||||
drive-strength = <8>;
|
||||
bias-pull-none;
|
||||
};
|
||||
};
|
||||
|
||||
ext_pri_tlmm_lines_sus: ext_pa_off {
|
||||
pinmux {
|
||||
function = "pri_mi2s";
|
||||
pins = "gpio113", "gpio114", "gpio115",
|
||||
"gpio116";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio113", "gpio114", "gpio115",
|
||||
"gpio116";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ext-pri-ws-line {
|
||||
ext_pri_ws_act: ext_pa_on {
|
||||
pinmux {
|
||||
function = "pri_mi2s_ws";
|
||||
pins = "gpio110";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio110";
|
||||
drive-strength = <8>;
|
||||
bias-pull-none;
|
||||
};
|
||||
};
|
||||
|
||||
ext_pri_ws_sus: ext_pa_off {
|
||||
pinmux {
|
||||
function = "pri_mi2s_ws";
|
||||
pins = "gpio110";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio110";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ext-mclk-tlmm-lines {
|
||||
ext_mclk_tlmm_lines_act: mclk_lines_on {
|
||||
pinmux {
|
||||
function = "pri_mi2s";
|
||||
pins = "gpio116";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio116";
|
||||
drive-strength = <8>;
|
||||
bias-pull-none;
|
||||
};
|
||||
};
|
||||
ext_mclk_tlmm_lines_sus: mclk_lines_off {
|
||||
pinmux {
|
||||
function = "pri_mi2s";
|
||||
pins = "gpio116";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio116";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* secondary Mi2S */
|
||||
ext-sec-tlmm-lines {
|
||||
ext_sec_tlmm_lines_act: tlmm_lines_on {
|
||||
pinmux {
|
||||
function = "sec_mi2s";
|
||||
pins = "gpio112", "gpio117", "gpio118",
|
||||
"gpio119";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio112", "gpio117", "gpio118",
|
||||
"gpio119";
|
||||
drive-strength = <8>;
|
||||
bias-pull-none;
|
||||
};
|
||||
};
|
||||
ext_sec_tlmm_lines_sus: tlmm_lines_off {
|
||||
pinmux {
|
||||
function = "sec_mi2s";
|
||||
pins = "gpio112", "gpio117", "gpio118",
|
||||
"gpio119";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio112", "gpio117", "gpio118",
|
||||
"gpio119";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cdc-dmic-lines {
|
||||
cdc_dmic_lines_act: dmic_lines_on {
|
||||
pinmux_dmic0_clk {
|
||||
function = "dmic0_clk";
|
||||
pins = "gpio0";
|
||||
};
|
||||
pinmux_dmic0_data {
|
||||
function = "dmic0_data";
|
||||
pins = "gpio1";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
};
|
||||
cdc_dmic_lines_sus: dmic_lines_off {
|
||||
pinconf {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cross-conn-det {
|
||||
cross_conn_det_act: lines_on {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio120";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio120";
|
||||
drive-strength = <8>;
|
||||
output-low;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
cross_conn_det_sus: lines_off {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio120";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio120";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,24 +61,33 @@
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -134,7 +143,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gcc: qcom,gcc@1800000 {
|
||||
gcc: clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-msm8916";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
|
@ -343,6 +352,32 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
lpass: lpass@07708000 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,lpass-cpu-apq8016";
|
||||
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
|
||||
<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
|
||||
<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
|
||||
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
|
||||
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
|
||||
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
|
||||
<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
|
||||
|
||||
clock-names = "ahbix-clk",
|
||||
"pcnoc-mport-clk",
|
||||
"pcnoc-sway-clk",
|
||||
"mi2s-bit-clk0",
|
||||
"mi2s-bit-clk1",
|
||||
"mi2s-bit-clk2",
|
||||
"mi2s-bit-clk3";
|
||||
#sound-dai-cells = <1>;
|
||||
|
||||
interrupts = <0 160 0>;
|
||||
interrupt-names = "lpass-irq-lpaif";
|
||||
reg = <0x07708000 0x10000>;
|
||||
reg-names = "lpass-lpaif";
|
||||
};
|
||||
|
||||
sdhc_1: sdhci@07824000 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
|
||||
|
|
@ -395,10 +430,11 @@
|
|||
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,vdd-levels = <1 5 7>;
|
||||
qcom,vdd-levels = <500000 1000000 1320000>;
|
||||
qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
|
||||
dr_mode = "peripheral";
|
||||
qcom,otg-control = <2>; // PMIC
|
||||
qcom,manual-pullup;
|
||||
|
||||
clocks = <&gcc GCC_USB_HS_AHB_CLK>,
|
||||
<&gcc GCC_USB_HS_SYSTEM_CLK>,
|
||||
|
|
@ -515,11 +551,15 @@
|
|||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
pm8916-regulators {
|
||||
rpmcc: qcom,rpmcc {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
smd_rpm_regulators: pm8916-regulators {
|
||||
compatible = "qcom,rpm-pm8916-regulators";
|
||||
|
||||
pm8916_s1: s1 {};
|
||||
pm8916_s2: s2 {};
|
||||
pm8916_s3: s3 {};
|
||||
pm8916_s4: s4 {};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8996-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. MSM 8996 MTP";
|
||||
compatible = "qcom,msm8996-mtp";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "msm8996.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &blsp2_uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
soc {
|
||||
serial@75b0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,269 @@
|
|||
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
|
||||
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. MSM8996";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/* We expect the bootloader to fill in the reg */
|
||||
reg = <0 0 0 0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
xo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
clock-output-names = "xo_board";
|
||||
};
|
||||
|
||||
sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32764>;
|
||||
clock-output-names = "sleep_clk";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@9bc0000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x09bc0000 0x10000>,
|
||||
<0x09c00000 0x100000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@300000 {
|
||||
compatible = "qcom,gcc-msm8996";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x300000 0x90000>;
|
||||
};
|
||||
|
||||
blsp2_uart1: serial@75b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x75b0000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl@1010000 {
|
||||
compatible = "qcom,msm8996-pinctrl";
|
||||
reg = <0x01010000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
timer@09840000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x09840000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@9850000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x09850000 0x1000>,
|
||||
<0x09860000 0x1000>;
|
||||
};
|
||||
|
||||
frame@9870000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x09870000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@9880000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x09880000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@9890000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x09890000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@98a0000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x098a0000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@98b0000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x098b0000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@98c0000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x098c0000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spmi_bus: qcom,spmi@400f000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0x400f000 0x1000>,
|
||||
<0x4400000 0x800000>,
|
||||
<0x4c00000 0x800000>,
|
||||
<0x5800000 0x200000>,
|
||||
<0x400a000 0x002100>;
|
||||
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
||||
interrupt-names = "periph_irq";
|
||||
interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
|
||||
qcom,ee = <0>;
|
||||
qcom,channel = <0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
};
|
||||
|
||||
mmcc: clock-controller@8c0000 {
|
||||
compatible = "qcom,mmcc-msm8996";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x8c0000 0x40000>;
|
||||
assigned-clocks = <&mmcc MMPLL9_PLL>,
|
||||
<&mmcc MMPLL1_PLL>,
|
||||
<&mmcc MMPLL3_PLL>,
|
||||
<&mmcc MMPLL4_PLL>,
|
||||
<&mmcc MMPLL5_PLL>;
|
||||
assigned-clock-rates = <624000000>,
|
||||
<810000000>,
|
||||
<980000000>,
|
||||
<960000000>,
|
||||
<825000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
|
||||
pmic@4 {
|
||||
compatible = "qcom,pm8004", "qcom,spmi-pmic";
|
||||
reg = <0x4 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pmic@5 {
|
||||
compatible = "qcom,pm8004", "qcom,spmi-pmic";
|
||||
reg = <0x5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
rtc@6000 {
|
||||
compatible = "qcom,pm8941-rtc";
|
||||
reg = <0x6000 0x6100>;
|
||||
reg = <0x6000>;
|
||||
reg-names = "rtc", "alarm";
|
||||
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
|
||||
pm8916_gpios: gpios@c000 {
|
||||
compatible = "qcom,pm8916-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
pm8916_mpps: mpps@a000 {
|
||||
compatible = "qcom,pm8916-mpp";
|
||||
reg = <0xa000 0x400>;
|
||||
reg = <0xa000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
|
||||
pm8916_temp: temp-alarm@2400 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0x2400 0x100>;
|
||||
reg = <0x2400>;
|
||||
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
|
||||
io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
|
||||
io-channel-names = "thermal";
|
||||
|
|
@ -58,7 +58,7 @@
|
|||
|
||||
pm8916_vadc: vadc@3100 {
|
||||
compatible = "qcom,spmi-vadc";
|
||||
reg = <0x3100 0x100>;
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
|
||||
pmic@0 {
|
||||
compatible = "qcom,pm8994", "qcom,spmi-pmic";
|
||||
reg = <0x0 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8994_gpios: gpios@c000 {
|
||||
compatible = "qcom,pm8994-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc5 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc6 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc7 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc8 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc9 0 IRQ_TYPE_NONE>,
|
||||
<0 0xca 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcb 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcc 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcd 0 IRQ_TYPE_NONE>,
|
||||
<0 0xce 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd5 0 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
pm8994_mpps: mpps@a000 {
|
||||
compatible = "qcom,pm8994-mpp";
|
||||
reg = <0xa000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa5 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa6 0 IRQ_TYPE_NONE>,
|
||||
<0 0xa7 0 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic@1 {
|
||||
compatible = "qcom,pm8994", "qcom,spmi-pmic";
|
||||
reg = <0x1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
|
||||
pmic@2 {
|
||||
compatible = "qcom,pmi8994", "qcom,spmi-pmic";
|
||||
reg = <0x2 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pmic@3 {
|
||||
compatible = "qcom,pmi8994", "qcom,spmi-pmic";
|
||||
reg = <0x3 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "r8a7795.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas Salvator-X board based on r8a7795";
|
||||
|
|
@ -61,6 +62,54 @@
|
|||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator@2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi3: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI3 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi3: regulator@4 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI3 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clkout: audio_clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
|
|
@ -93,6 +142,9 @@
|
|||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif1_pins: scif1 {
|
||||
renesas,groups = "scif1_data_a", "scif1_ctrl";
|
||||
renesas,function = "scif1";
|
||||
|
|
@ -101,6 +153,10 @@
|
|||
renesas,groups = "scif2_data_a";
|
||||
renesas,function = "scif2";
|
||||
};
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk_a";
|
||||
renesas,function = "scif_clk";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
renesas,groups = "i2c2_a";
|
||||
|
|
@ -112,6 +168,16 @@
|
|||
renesas,function = "avb";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi3_pins: sd3 {
|
||||
renesas,groups = "sdhi3_data4", "sdhi3_ctrl";
|
||||
renesas,function = "sdhi3";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
renesas,groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
|
||||
renesas,function = "ssi";
|
||||
|
|
@ -122,6 +188,16 @@
|
|||
"audio_clkout_a", "audio_clkout3_a";
|
||||
renesas,function = "audio_clk";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
renesas,groups = "usb1";
|
||||
renesas,function = "usb1";
|
||||
};
|
||||
|
||||
usb2_pins: usb2 {
|
||||
renesas,groups = "usb2";
|
||||
renesas,function = "usb2";
|
||||
};
|
||||
};
|
||||
|
||||
&scif1 {
|
||||
|
|
@ -138,6 +214,11 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -216,6 +297,30 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi3>;
|
||||
vqmmc-supply = <&vccq_sdhi3>;
|
||||
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
|
@ -249,3 +354,37 @@
|
|||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&xhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@
|
|||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
|
|
@ -46,22 +47,37 @@
|
|||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
a57_2: cpu@2 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x2>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
a57_3: cpu@3 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x3>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller@1 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -99,6 +115,14 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -113,7 +137,9 @@
|
|||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x2000>;
|
||||
<0x0 0xf1020000 0 0x2000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
|
@ -230,8 +256,8 @@
|
|||
power-domains = <&cpg>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
pmu_a57 {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -266,23 +292,23 @@
|
|||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xec700000 0 0x10000>;
|
||||
interrupts = <0 350 IRQ_TYPE_LEVEL_HIGH
|
||||
0 320 IRQ_TYPE_LEVEL_HIGH
|
||||
0 321 IRQ_TYPE_LEVEL_HIGH
|
||||
0 322 IRQ_TYPE_LEVEL_HIGH
|
||||
0 323 IRQ_TYPE_LEVEL_HIGH
|
||||
0 324 IRQ_TYPE_LEVEL_HIGH
|
||||
0 325 IRQ_TYPE_LEVEL_HIGH
|
||||
0 326 IRQ_TYPE_LEVEL_HIGH
|
||||
0 327 IRQ_TYPE_LEVEL_HIGH
|
||||
0 328 IRQ_TYPE_LEVEL_HIGH
|
||||
0 329 IRQ_TYPE_LEVEL_HIGH
|
||||
0 330 IRQ_TYPE_LEVEL_HIGH
|
||||
0 331 IRQ_TYPE_LEVEL_HIGH
|
||||
0 332 IRQ_TYPE_LEVEL_HIGH
|
||||
0 333 IRQ_TYPE_LEVEL_HIGH
|
||||
0 334 IRQ_TYPE_LEVEL_HIGH
|
||||
0 335 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
|
|
@ -298,23 +324,23 @@
|
|||
audma1: dma-controller@ec720000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xec720000 0 0x10000>;
|
||||
interrupts = <0 351 IRQ_TYPE_LEVEL_HIGH
|
||||
0 336 IRQ_TYPE_LEVEL_HIGH
|
||||
0 337 IRQ_TYPE_LEVEL_HIGH
|
||||
0 338 IRQ_TYPE_LEVEL_HIGH
|
||||
0 339 IRQ_TYPE_LEVEL_HIGH
|
||||
0 340 IRQ_TYPE_LEVEL_HIGH
|
||||
0 341 IRQ_TYPE_LEVEL_HIGH
|
||||
0 342 IRQ_TYPE_LEVEL_HIGH
|
||||
0 343 IRQ_TYPE_LEVEL_HIGH
|
||||
0 344 IRQ_TYPE_LEVEL_HIGH
|
||||
0 345 IRQ_TYPE_LEVEL_HIGH
|
||||
0 346 IRQ_TYPE_LEVEL_HIGH
|
||||
0 347 IRQ_TYPE_LEVEL_HIGH
|
||||
0 348 IRQ_TYPE_LEVEL_HIGH
|
||||
0 349 IRQ_TYPE_LEVEL_HIGH
|
||||
0 382 IRQ_TYPE_LEVEL_HIGH
|
||||
0 383 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
|
|
@ -332,20 +358,123 @@
|
|||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&cpg>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
/* Empty node for now */
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
/* Empty node for now */
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
/* Empty node for now */
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a7795";
|
||||
compatible = "renesas,etheravb-r8a7795",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -387,11 +516,15 @@
|
|||
};
|
||||
|
||||
hscif0: serial@e6540000 {
|
||||
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
"renesas,hscif";
|
||||
reg = <0 0xe6540000 0 96>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 520>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 520>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -399,11 +532,15 @@
|
|||
};
|
||||
|
||||
hscif1: serial@e6550000 {
|
||||
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
"renesas,hscif";
|
||||
reg = <0 0xe6550000 0 96>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 519>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 519>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -411,11 +548,15 @@
|
|||
};
|
||||
|
||||
hscif2: serial@e6560000 {
|
||||
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
"renesas,hscif";
|
||||
reg = <0 0xe6560000 0 96>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 518>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 518>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -423,11 +564,15 @@
|
|||
};
|
||||
|
||||
hscif3: serial@e66a0000 {
|
||||
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
"renesas,hscif";
|
||||
reg = <0 0xe66a0000 0 96>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 517>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 517>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -435,11 +580,15 @@
|
|||
};
|
||||
|
||||
hscif4: serial@e66b0000 {
|
||||
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
"renesas,hscif";
|
||||
reg = <0 0xe66b0000 0 96>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 516>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 516>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -447,11 +596,14 @@
|
|||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e60000 0 64>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 207>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 207>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -459,11 +611,14 @@
|
|||
};
|
||||
|
||||
scif1: serial@e6e68000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e68000 0 64>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 206>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 206>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -471,11 +626,14 @@
|
|||
};
|
||||
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 310>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -483,11 +641,14 @@
|
|||
};
|
||||
|
||||
scif3: serial@e6c50000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6c50000 0 64>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 204>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 204>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -495,11 +656,14 @@
|
|||
};
|
||||
|
||||
scif4: serial@e6c40000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6c40000 0 64>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 203>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 203>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -507,11 +671,14 @@
|
|||
};
|
||||
|
||||
scif5: serial@e6f30000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6f30000 0 64>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 202>;
|
||||
clock-names = "sci_ick";
|
||||
clocks = <&cpg CPG_MOD 202>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
|
@ -663,52 +830,52 @@
|
|||
|
||||
rcar_sound,src {
|
||||
src0: src@0 {
|
||||
interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x85>, <&audma1 0x9a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src1: src@1 {
|
||||
interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x87>, <&audma1 0x9c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src2: src@2 {
|
||||
interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x89>, <&audma1 0x9e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src3: src@3 {
|
||||
interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src4: src@4 {
|
||||
interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src5: src@5 {
|
||||
interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src6: src@6 {
|
||||
interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x91>, <&audma1 0xb4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src7: src@7 {
|
||||
interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x93>, <&audma1 0xb6>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src8: src@8 {
|
||||
interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x95>, <&audma1 0xb8>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src9: src@9 {
|
||||
interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x97>, <&audma1 0xba>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
|
@ -716,52 +883,52 @@
|
|||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi@0 {
|
||||
interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi1: ssi@1 {
|
||||
interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi2: ssi@2 {
|
||||
interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi3: ssi@3 {
|
||||
interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi4: ssi@4 {
|
||||
interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi5: ssi@5 {
|
||||
interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi6: ssi@6 {
|
||||
interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi7: ssi@7 {
|
||||
interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi8: ssi@8 {
|
||||
interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi9: ssi@9 {
|
||||
interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
|
|
@ -775,5 +942,181 @@
|
|||
clocks = <&cpg CPG_MOD 815>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
compatible = "renesas,xhci-r8a7795";
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 328>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci1: usb@ee0400000 {
|
||||
compatible = "renesas,xhci-r8a7795";
|
||||
reg = <0 0xee040000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 327>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 330>;
|
||||
power-domains = <&cpg>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac1: dma-controller@e65b0000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65b0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 331>;
|
||||
power-domains = <&cpg>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
power-domains = <&cpg>;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
power-domains = <&cpg>;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@ee080200 {
|
||||
compatible = "renesas,usb2-phy-r8a7795";
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
power-domains = <&cpg>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy1: usb-phy@ee0a0200 {
|
||||
compatible = "renesas,usb2-phy-r8a7795";
|
||||
reg = <0 0xee0a0200 0 0x700>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
power-domains = <&cpg>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy2: usb-phy@ee0c0200 {
|
||||
compatible = "renesas,usb2-phy-r8a7795";
|
||||
reg = <0 0xee0c0200 0 0x700>;
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
power-domains = <&cpg>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@ee0a0100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee0a0100 0 0x100>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci2: usb@ee0c0100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee0c0100 0 0x100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@ee0a0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci2: usb@ee0c0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0c0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@
|
|||
pinctrl-0 = <&pwr_key>;
|
||||
|
||||
button@0 {
|
||||
gpio-key,wakeup = <1>;
|
||||
wakeup-source;
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Power";
|
||||
linux,code = <116>;
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@
|
|||
pinctrl-0 = <&pwr_key>;
|
||||
|
||||
button@0 {
|
||||
gpio-key,wakeup = <1>;
|
||||
wakeup-source;
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Power";
|
||||
linux,code = <116>;
|
||||
|
|
|
|||
|
|
@ -231,8 +231,9 @@
|
|||
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xff0c0000 0x0 0x4000>;
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
|
|
@ -254,8 +255,9 @@
|
|||
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xff0f0000 0x0 0x4000>;
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* clock specification for Xilinx ZynqMP ep108 development board
|
||||
*
|
||||
* (C) Copyright 2015, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
&amba {
|
||||
misc_clk: misc_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c_clk: i2c_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x0>;
|
||||
clock-frequency = <111111111>;
|
||||
};
|
||||
|
||||
sata_clk: sata_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <75000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
clocks = <&misc_clk>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&i2c_clk>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&i2c_clk>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
clocks = <&sata_clk>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
clocks= <&misc_clk>;
|
||||
};
|
||||
|
|
@ -14,6 +14,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "zynqmp.dtsi"
|
||||
/include/ "zynqmp-ep108-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP EP108";
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
amba {
|
||||
amba: amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -99,7 +99,6 @@
|
|||
can0: can@ff060000 {
|
||||
compatible = "xlnx,zynq-can-1.0";
|
||||
status = "disabled";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
clock-names = "can_clk", "pclk";
|
||||
reg = <0x0 0xff060000 0x1000>;
|
||||
interrupts = <0 23 4>;
|
||||
|
|
@ -111,7 +110,6 @@
|
|||
can1: can@ff070000 {
|
||||
compatible = "xlnx,zynq-can-1.0";
|
||||
status = "disabled";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
clock-names = "can_clk", "pclk";
|
||||
reg = <0x0 0xff070000 0x1000>;
|
||||
interrupts = <0 24 4>;
|
||||
|
|
@ -120,24 +118,6 @@
|
|||
rx-fifo-depth = <0x40>;
|
||||
};
|
||||
|
||||
misc_clk: misc_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
gpio: gpio@ff0a0000 {
|
||||
compatible = "xlnx,zynqmp-gpio-1.0";
|
||||
status = "disabled";
|
||||
#gpio-cells = <0x2>;
|
||||
clocks = <&misc_clk>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0xff0a0000 0x1000>;
|
||||
};
|
||||
|
||||
gem0: ethernet@ff0b0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
|
|
@ -145,7 +125,6 @@
|
|||
interrupts = <0 57 4>, <0 57 4>;
|
||||
reg = <0x0 0xff0b0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -157,7 +136,6 @@
|
|||
interrupts = <0 59 4>, <0 59 4>;
|
||||
reg = <0x0 0xff0c0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -169,7 +147,6 @@
|
|||
interrupts = <0 61 4>, <0 61 4>;
|
||||
reg = <0x0 0xff0d0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -181,15 +158,19 @@
|
|||
interrupts = <0 63 4>, <0 63 4>;
|
||||
reg = <0x0 0xff0e0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c_clk: i2c_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x0>;
|
||||
clock-frequency = <111111111>;
|
||||
gpio: gpio@ff0a0000 {
|
||||
compatible = "xlnx,zynqmp-gpio-1.0";
|
||||
status = "disabled";
|
||||
#gpio-cells = <0x2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0xff0a0000 0x1000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
|
|
@ -198,7 +179,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 17 4>;
|
||||
reg = <0x0 0xff020000 0x1000>;
|
||||
clocks = <&i2c_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -209,24 +189,16 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 18 4>;
|
||||
reg = <0x0 0xff030000 0x1000>;
|
||||
clocks = <&i2c_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
sata_clk: sata_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <75000000>;
|
||||
};
|
||||
|
||||
sata: ahci@fd0c0000 {
|
||||
compatible = "ceva,ahci-1v84";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd0c0000 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 133 4>;
|
||||
clocks = <&sata_clk>;
|
||||
};
|
||||
|
||||
sdhci0: sdhci@ff160000 {
|
||||
|
|
@ -236,7 +208,6 @@
|
|||
interrupts = <0 48 4>;
|
||||
reg = <0x0 0xff160000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
sdhci1: sdhci@ff170000 {
|
||||
|
|
@ -246,7 +217,6 @@
|
|||
interrupts = <0 49 4>;
|
||||
reg = <0x0 0xff170000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
smmu: smmu@fd800000 {
|
||||
|
|
@ -268,7 +238,6 @@
|
|||
interrupts = <0 19 4>;
|
||||
reg = <0x0 0xff040000 0x1000>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -280,7 +249,6 @@
|
|||
interrupts = <0 20 4>;
|
||||
reg = <0x0 0xff050000 0x1000>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -291,7 +259,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
reg = <0x0 0xff110000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
|
|
@ -301,7 +268,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
|
||||
reg = <0x0 0xff120000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
|
|
@ -311,7 +277,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
|
||||
reg = <0x0 0xff130000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
|
|
@ -321,7 +286,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
|
||||
reg = <0x0 0xff140000 0x1000>;
|
||||
clocks = <&misc_clk>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
|
|
@ -332,7 +296,6 @@
|
|||
interrupts = <0 21 4>;
|
||||
reg = <0x0 0xff000000 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
|
|
@ -342,7 +305,6 @@
|
|||
interrupts = <0 22 4>;
|
||||
reg = <0x0 0xff010000 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
usb0: usb@fe200000 {
|
||||
|
|
@ -352,7 +314,6 @@
|
|||
interrupts = <0 65 4>;
|
||||
reg = <0x0 0xfe200000 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
usb1: usb@fe300000 {
|
||||
|
|
@ -362,13 +323,11 @@
|
|||
interrupts = <0 70 4>;
|
||||
reg = <0x0 0xfe300000 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
watchdog0: watchdog@fd4d0000 {
|
||||
compatible = "cdns,wdt-r1p2";
|
||||
status = "disabled";
|
||||
clocks= <&misc_clk>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 52 1>;
|
||||
reg = <0x0 0xfd4d0000 0x1000>;
|
||||
|
|
|
|||
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