[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
Родитель
90b02340dc
Коммит
91a2fcc886
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@ -65,8 +65,6 @@
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#define EXT_INTC1_REQ1 5 /* IP 5 */
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#define MIPS_TIMER_IP 7 /* IP 7 */
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extern void mips_timer_interrupt(void);
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void (*board_init_irq)(void);
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static DEFINE_SPINLOCK(irq_lock);
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@ -635,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void)
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & CAUSEF_IP7)
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mips_timer_interrupt();
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ll_timer_interrupt(63);
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else if (pending & CAUSEF_IP2)
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intc0_req0_irqdispatch();
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else if (pending & CAUSEF_IP3)
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@ -64,48 +64,8 @@ static unsigned long last_pc0, last_match20;
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static DEFINE_SPINLOCK(time_lock);
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static inline void ack_r4ktimer(unsigned long newval)
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{
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write_c0_compare(newval);
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}
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/*
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* There are a lot of conceptually broken versions of the MIPS timer interrupt
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* handler floating around. This one is rather different, but the algorithm
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* is provably more robust.
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*/
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unsigned long wtimer;
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void mips_timer_interrupt(void)
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{
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int irq = 63;
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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if (r4k_offset == 0)
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goto null;
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do {
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kstat_this_cpu.irqs[irq]++;
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do_timer(1);
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#ifndef CONFIG_SMP
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update_process_times(user_mode(get_irq_regs()));
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#endif
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r4k_cur += r4k_offset;
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ack_r4ktimer(r4k_cur);
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} while (((unsigned long)read_c0_count()
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- r4k_cur) < 0x7fffffff);
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irq_exit();
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return;
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null:
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ack_r4ktimer(0);
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irq_exit();
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}
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#ifdef CONFIG_PM
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irqreturn_t counter0_irq(int irq, void *dev_id)
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{
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@ -867,7 +867,7 @@ void ipi_decode(struct smtc_ipi *pipi)
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
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clock_hang_reported[dest_copy] = 0;
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#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
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local_timer_interrupt(0, NULL);
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local_timer_interrupt(0);
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irq_exit();
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break;
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case LINUX_SMP_IPI:
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@ -144,7 +144,7 @@ void local_timer_interrupt(int irq, void *dev_id)
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* High-level timer interrupt service routines. This function
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* is set as irqaction->handler and is invoked through do_IRQ.
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*/
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irqreturn_t timer_interrupt(int irq, void *dev_id)
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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write_seqlock(&xtime_lock);
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@ -174,9 +174,10 @@ int null_perf_irq(void)
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return 0;
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}
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EXPORT_SYMBOL(null_perf_irq);
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int (*perf_irq)(void) = null_perf_irq;
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EXPORT_SYMBOL(null_perf_irq);
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EXPORT_SYMBOL(perf_irq);
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/*
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@ -208,35 +209,79 @@ static inline int handle_perf_irq (int r2)
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!r2;
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}
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asmlinkage void ll_timer_interrupt(int irq)
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void ll_timer_interrupt(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* In an SMTC system, one Count/Compare set exists per VPE.
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* Which TC within a VPE gets the interrupt is essentially
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* random - we only know that it shouldn't be one with
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* IXMT set. Whichever TC gets the interrupt needs to
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* send special interprocessor interrupts to the other
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* TCs to make sure that they schedule, etc.
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*
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* That code is specific to the SMTC kernel, not to
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* the a particular platform, so it's invoked from
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* the general MIPS timer_interrupt routine.
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*/
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/*
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* We could be here due to timer interrupt,
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* perf counter overflow, or both.
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*/
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(void) handle_perf_irq(1);
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if (read_c0_cause() & (1 << 30)) {
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/*
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* There are things we only want to do once per tick
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* in an "MP" system. One TC of each VPE will take
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* the actual timer interrupt. The others will get
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* timer broadcast IPIs. We use whoever it is that takes
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* the tick on VPE 0 to run the full timer_interrupt().
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*/
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if (cpu_data[cpu].vpe_id == 0) {
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timer_interrupt(irq, NULL);
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} else {
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write_c0_compare(read_c0_count() +
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(mips_hpt_frequency/HZ));
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local_timer_interrupt(irq, dev_id);
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}
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smtc_timer_broadcast(cpu_data[cpu].vpe_id);
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}
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#else /* CONFIG_MIPS_MT_SMTC */
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int r2 = cpu_has_mips_r2;
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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if (handle_perf_irq(r2))
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goto out;
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return;
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if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
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goto out;
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return;
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timer_interrupt(irq, NULL);
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if (cpu == 0) {
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/*
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* CPU 0 handles the global timer interrupt job and process
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* accounting resets count/compare registers to trigger next
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* timer int.
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*/
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timer_interrupt(irq, NULL);
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} else {
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/* Everyone else needs to reset the timer int here as
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ll_local_timer_interrupt doesn't */
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/*
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* FIXME: need to cope with counter underflow.
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* More support needs to be added to kernel/time for
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* counter/timer interrupts on multiple CPU's
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*/
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write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
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out:
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irq_exit();
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}
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asmlinkage void ll_local_timer_interrupt(int irq)
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{
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irq_enter();
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if (smp_processor_id() != 0)
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kstat_this_cpu.irqs[irq]++;
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/* we keep interrupt disabled all the time */
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local_timer_interrupt(irq, NULL);
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irq_exit();
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/*
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* Other CPUs should do profiling and process accounting
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*/
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local_timer_interrupt(irq, dev_id);
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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/*
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@ -67,108 +67,6 @@ static void mips_perf_dispatch(void)
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do_IRQ(cp0_perfcount_irq);
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}
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/*
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* Redeclare until I get around mopping the timer code insanity on MIPS.
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*/
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extern int null_perf_irq(void);
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extern int (*perf_irq)(void);
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/*
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* Possibly handle a performance counter interrupt.
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* Return true if the timer interrupt should not be checked
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*/
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static inline int handle_perf_irq (int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* In an SMTC system, one Count/Compare set exists per VPE.
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* Which TC within a VPE gets the interrupt is essentially
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* random - we only know that it shouldn't be one with
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* IXMT set. Whichever TC gets the interrupt needs to
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* send special interprocessor interrupts to the other
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* TCs to make sure that they schedule, etc.
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*
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* That code is specific to the SMTC kernel, not to
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* the a particular platform, so it's invoked from
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* the general MIPS timer_interrupt routine.
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*/
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/*
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* We could be here due to timer interrupt,
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* perf counter overflow, or both.
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*/
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(void) handle_perf_irq(1);
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if (read_c0_cause() & (1 << 30)) {
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/*
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* There are things we only want to do once per tick
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* in an "MP" system. One TC of each VPE will take
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* the actual timer interrupt. The others will get
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* timer broadcast IPIs. We use whoever it is that takes
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* the tick on VPE 0 to run the full timer_interrupt().
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*/
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if (cpu_data[cpu].vpe_id == 0) {
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timer_interrupt(irq, NULL);
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} else {
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write_c0_compare(read_c0_count() +
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(mips_hpt_frequency/HZ));
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local_timer_interrupt(irq, dev_id);
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}
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smtc_timer_broadcast();
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}
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#else /* CONFIG_MIPS_MT_SMTC */
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int r2 = cpu_has_mips_r2;
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if (handle_perf_irq(r2))
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goto out;
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if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
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goto out;
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if (cpu == 0) {
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/*
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* CPU 0 handles the global timer interrupt job and process
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* accounting resets count/compare registers to trigger next
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* timer int.
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*/
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timer_interrupt(irq, NULL);
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} else {
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/* Everyone else needs to reset the timer int here as
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ll_local_timer_interrupt doesn't */
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/*
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* FIXME: need to cope with counter underflow.
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* More support needs to be added to kernel/time for
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* counter/timer interrupts on multiple CPU's
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*/
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write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
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/*
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* Other CPUs should do profiling and process accounting
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*/
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local_timer_interrupt(irq, dev_id);
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}
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out:
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#endif /* CONFIG_MIPS_MT_SMTC */
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return IRQ_HANDLED;
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}
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/*
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* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
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*/
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@ -246,7 +144,7 @@ void __init plat_time_init(void)
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mips_scroll_message();
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}
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irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
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static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
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{
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return perf_irq();
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}
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@ -257,8 +155,10 @@ static struct irqaction perf_irqaction = {
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.name = "performance",
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};
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void __init plat_perf_setup(struct irqaction *irq)
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void __init plat_perf_setup(void)
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{
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struct irqaction *irq = &perf_irqaction;
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cp0_perfcount_irq = -1;
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#ifdef MSC01E_INT_BASE
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@ -297,8 +197,6 @@ void __init plat_timer_setup(struct irqaction *irq)
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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/* we are using the cpu counter for timer interrupts */
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irq->handler = mips_timer_interrupt; /* we use our own handler */
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
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#else
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@ -308,5 +206,5 @@ void __init plat_timer_setup(struct irqaction *irq)
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set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
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#endif
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plat_perf_setup(&perf_irqaction);
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plat_perf_setup();
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}
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@ -23,77 +23,6 @@
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unsigned long cpu_khz;
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irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
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{
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#ifdef CONFIG_SMP
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int cpu = smp_processor_id();
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/*
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* CPU 0 handles the global timer interrupt job
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* resets count/compare registers to trigger next timer int.
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*/
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#ifndef CONFIG_MIPS_MT_SMTC
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if (cpu == 0) {
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timer_interrupt(irq, dev_id);
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} else {
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/* Everyone else needs to reset the timer int here as
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ll_local_timer_interrupt doesn't */
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/*
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* FIXME: need to cope with counter underflow.
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* More support needs to be added to kernel/time for
|
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* counter/timer interrupts on multiple CPU's
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*/
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write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
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}
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#else /* SMTC */
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/*
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* In SMTC system, one Count/Compare set exists per VPE.
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* Which TC within a VPE gets the interrupt is essentially
|
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* random - we only know that it shouldn't be one with
|
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* IXMT set. Whichever TC gets the interrupt needs to
|
||||
* send special interprocessor interrupts to the other
|
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* TCs to make sure that they schedule, etc.
|
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*
|
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* That code is specific to the SMTC kernel, not to
|
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* the simulation platform, so it's invoked from
|
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* the general MIPS timer_interrupt routine.
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*
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* We have a problem in that the interrupt vector code
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* had to turn off the timer IM bit to avoid redundant
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* entries, but we may never get to mips_cpu_irq_end
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* to turn it back on again if the scheduler gets
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* involved. So we clear the pending timer here,
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* and re-enable the mask...
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*/
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int vpflags = dvpe();
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write_c0_compare (read_c0_count() - 1);
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clear_c0_cause(0x100 << cp0_compare_irq);
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set_c0_status(0x100 << cp0_compare_irq);
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irq_enable_hazard();
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evpe(vpflags);
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if (cpu_data[cpu].vpe_id == 0)
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timer_interrupt(irq, dev_id);
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else
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write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
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smtc_timer_broadcast(cpu_data[cpu].vpe_id);
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#endif /* CONFIG_MIPS_MT_SMTC */
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/*
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* every CPU should do profiling and process accounting
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*/
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local_timer_interrupt (irq, dev_id);
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return IRQ_HANDLED;
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#else
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return timer_interrupt (irq, dev_id);
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#endif
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}
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/*
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* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
|
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*/
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|
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@ -185,7 +114,6 @@ void __init plat_timer_setup(struct irqaction *irq)
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}
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/* we are using the cpu counter for timer interrupts */
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irq->handler = sim_timer_interrupt;
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setup_irq(mips_cpu_timer_irq, irq);
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#ifdef CONFIG_SMP
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|
|
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@ -20,10 +20,10 @@
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/irq_cpu.h>
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#include <asm/sgi/ioc.h>
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#include <asm/sgi/hpc3.h>
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#include <asm/sgi/ip22.h>
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#include <asm/time.h>
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/* #define DEBUG_SGINT */
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@ -204,7 +204,6 @@ static struct irqaction map1_cascade = {
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#define SGI_INTERRUPTS SGINT_LOCAL3
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#endif
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extern void indy_r4k_timer_interrupt(void);
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extern void indy_8254timer_irq(void);
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/*
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|
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@ -243,7 +242,7 @@ asmlinkage void plat_irq_dispatch(void)
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* First we check for r4k counter/timer IRQ.
|
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*/
|
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if (pending & CAUSEF_IP7)
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indy_r4k_timer_interrupt();
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ll_timer_interrupt(SGI_TIMER_IRQ, NULL);
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else if (pending & CAUSEF_IP2)
|
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indy_local0_irqdispatch();
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else if (pending & CAUSEF_IP3)
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|
|
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|
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@ -189,16 +189,6 @@ void indy_8254timer_irq(void)
|
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irq_exit();
|
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}
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void indy_r4k_timer_interrupt(void)
|
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{
|
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int irq = SGI_TIMER_IRQ;
|
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|
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irq_enter();
|
||||
kstat_this_cpu.irqs[irq]++;
|
||||
timer_interrupt(irq, NULL);
|
||||
irq_exit();
|
||||
}
|
||||
|
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void __init plat_timer_setup(struct irqaction *irq)
|
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{
|
||||
/* over-write the handler, we use our own way */
|
||||
|
|
|
|||
|
|
@ -103,18 +103,7 @@ void bcm1480_timer_interrupt(void)
|
|||
__raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
|
||||
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
|
||||
|
||||
if (cpu == 0) {
|
||||
/*
|
||||
* CPU 0 handles the global timer interrupt job
|
||||
*/
|
||||
ll_timer_interrupt(irq);
|
||||
}
|
||||
else {
|
||||
/*
|
||||
* other CPUs should just do profiling and process accounting
|
||||
*/
|
||||
ll_local_timer_interrupt(irq);
|
||||
}
|
||||
ll_timer_interrupt(irq);
|
||||
}
|
||||
|
||||
static cycle_t bcm1480_hpt_read(void)
|
||||
|
|
|
|||
|
|
@ -125,18 +125,7 @@ void sb1250_timer_interrupt(void)
|
|||
____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
|
||||
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
|
||||
|
||||
if (cpu == 0) {
|
||||
/*
|
||||
* CPU 0 handles the global timer interrupt job
|
||||
*/
|
||||
ll_timer_interrupt(irq);
|
||||
}
|
||||
else {
|
||||
/*
|
||||
* other CPUs should just do profiling and process accounting
|
||||
*/
|
||||
ll_local_timer_interrupt(irq);
|
||||
}
|
||||
ll_timer_interrupt(irq);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -49,20 +49,14 @@ extern void (*mips_timer_ack)(void);
|
|||
extern struct clocksource clocksource_mips;
|
||||
|
||||
/*
|
||||
* high-level timer interrupt routines.
|
||||
* The low-level timer interrupt routine.
|
||||
*/
|
||||
extern irqreturn_t timer_interrupt(int irq, void *dev_id);
|
||||
|
||||
/*
|
||||
* the corresponding low-level timer interrupt routine.
|
||||
*/
|
||||
extern asmlinkage void ll_timer_interrupt(int irq);
|
||||
extern void ll_timer_interrupt(int irq, void *dev_id);
|
||||
|
||||
/*
|
||||
* profiling and process accouting is done separately in local_timer_interrupt
|
||||
*/
|
||||
extern void local_timer_interrupt(int irq, void *dev_id);
|
||||
extern asmlinkage void ll_local_timer_interrupt(int irq);
|
||||
|
||||
/*
|
||||
* board specific routines required by time_init().
|
||||
|
|
@ -78,4 +72,10 @@ extern void plat_timer_setup(struct irqaction *irq);
|
|||
*/
|
||||
extern unsigned int mips_hpt_frequency;
|
||||
|
||||
/*
|
||||
* The performance counter IRQ on MIPS is a close relative to the timer IRQ
|
||||
* so it lives here.
|
||||
*/
|
||||
extern int (*perf_irq)(void);
|
||||
|
||||
#endif /* _ASM_TIME_H */
|
||||
|
|
|
|||
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