m68knommu: m528x build fix
There isn't any mcfqspi.h in the tree, and without it everything inside the #ifdef CONFIG_SPI is uncompilable. Signed-off-by: Steven King <sfking@fdwdc.com> Acked-by: Greg Ungerer <gerg@snapgear.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Steven King
Linus Torvalds
Родитель
9333d82681
Коммит
9233ecc5c4
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@ -24,7 +24,6 @@
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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#ifdef CONFIG_MTD_PARTITIONS
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#include <linux/mtd/partitions.h>
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@ -33,233 +32,6 @@
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/***************************************************************************/
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void coldfire_reset(void);
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static void coldfire_qspi_cs_control(u8 cs, u8 command);
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/***************************************************************************/
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#if defined(CONFIG_SPI)
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#if defined(CONFIG_WILDFIRE)
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#define SPI_NUM_CHIPSELECTS 0x02
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#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
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#define SPI_CS_MASK 0x18
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#define FLASH_BLOCKSIZE (1024*64)
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#define FLASH_NUMBLOCKS 16
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#define FLASH_TYPE "m25p80"
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#define M25P80_CS 0
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#define MMC_CS 1
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition stm25p_partitions[] = {
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/* sflash */
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[0] = {
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.name = "stm25p80",
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.offset = 0x00000000,
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.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
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.mask_flags = 0
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}
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};
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#endif
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#elif defined(CONFIG_WILDFIREMOD)
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#define SPI_NUM_CHIPSELECTS 0x08
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#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
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#define SPI_CS_MASK 0x78
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#define FLASH_BLOCKSIZE (1024*64)
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#define FLASH_NUMBLOCKS 64
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#define FLASH_TYPE "m25p32"
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/* Reserve 1M for the kernel parition */
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#define FLASH_KERNEL_SIZE (1024 * 1024)
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#define M25P80_CS 5
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#define MMC_CS 6
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition stm25p_partitions[] = {
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/* sflash */
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[0] = {
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.name = "kernel",
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.offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
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.size = FLASH_KERNEL_SIZE,
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.mask_flags = 0
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},
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[1] = {
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.name = "image",
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.offset = 0x00000000,
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.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
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.mask_flags = 0
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},
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[2] = {
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.name = "all",
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.offset = 0x00000000,
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.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
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.mask_flags = 0
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}
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};
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#endif
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#else
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#define SPI_NUM_CHIPSELECTS 0x04
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#define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */
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#endif
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#ifdef MMC_CS
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static struct coldfire_spi_chip flash_chip_info = {
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.mode = SPI_MODE_0,
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.bits_per_word = 16,
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.del_cs_to_clk = 17,
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.del_after_trans = 1,
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.void_write_data = 0
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};
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static struct coldfire_spi_chip mmc_chip_info = {
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.mode = SPI_MODE_0,
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.bits_per_word = 16,
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.del_cs_to_clk = 17,
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.del_after_trans = 1,
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.void_write_data = 0xFFFF
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};
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#endif
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#ifdef M25P80_CS
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static struct flash_platform_data stm25p80_platform_data = {
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.name = "ST M25P80 SPI Flash chip",
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#ifdef CONFIG_MTD_PARTITIONS
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.parts = stm25p_partitions,
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.nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions),
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#endif
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.type = FLASH_TYPE
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};
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#endif
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static struct spi_board_info spi_board_info[] __initdata = {
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#ifdef M25P80_CS
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{
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.modalias = "m25p80",
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.max_speed_hz = 16000000,
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.bus_num = 1,
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.chip_select = M25P80_CS,
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.platform_data = &stm25p80_platform_data,
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.controller_data = &flash_chip_info
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},
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#endif
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#ifdef MMC_CS
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{
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.modalias = "mmc_spi",
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.max_speed_hz = 16000000,
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.bus_num = 1,
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.chip_select = MMC_CS,
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.controller_data = &mmc_chip_info
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}
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#endif
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};
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static struct coldfire_spi_master coldfire_master_info = {
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.bus_num = 1,
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.num_chipselect = SPI_NUM_CHIPSELECTS,
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.irq_source = MCF5282_QSPI_IRQ_SOURCE,
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.irq_vector = MCF5282_QSPI_IRQ_VECTOR,
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.irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01),
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.irq_lp = 0x2B, /* Level 5 and Priority 3 */
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.par_val = SPI_PAR_VAL,
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.cs_control = coldfire_qspi_cs_control,
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};
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static struct resource coldfire_spi_resources[] = {
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[0] = {
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.name = "qspi-par",
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.start = MCF5282_QSPI_PAR,
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.end = MCF5282_QSPI_PAR,
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.flags = IORESOURCE_MEM
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},
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[1] = {
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.name = "qspi-module",
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.start = MCF5282_QSPI_QMR,
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.end = MCF5282_QSPI_QMR + 0x18,
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.flags = IORESOURCE_MEM
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},
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[2] = {
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.name = "qspi-int-level",
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.start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
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.end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
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.flags = IORESOURCE_MEM
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},
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[3] = {
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.name = "qspi-int-mask",
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.start = MCF5282_INTC0 + MCFINTC_IMRL,
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.end = MCF5282_INTC0 + MCFINTC_IMRL,
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.flags = IORESOURCE_MEM
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}
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};
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static struct platform_device coldfire_spi = {
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.name = "spi_coldfire",
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.id = -1,
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.resource = coldfire_spi_resources,
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.num_resources = ARRAY_SIZE(coldfire_spi_resources),
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.dev = {
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.platform_data = &coldfire_master_info,
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}
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};
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static void coldfire_qspi_cs_control(u8 cs, u8 command)
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{
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u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK;
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#if defined(CONFIG_WILDFIRE)
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u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK);
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#endif
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#if defined(CONFIG_WILDFIREMOD)
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u8 cs_mask = (cs << 3) & SPI_CS_MASK;
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#endif
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/*
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* Don't do anything if the chip select is not
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* one of the port qs pins.
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*/
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if (command & QSPI_CS_INIT) {
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#if defined(CONFIG_WILDFIRE)
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MCF5282_GPIO_DDRQS |= cs_bit;
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MCF5282_GPIO_PQSPAR &= ~cs_bit;
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#endif
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#if defined(CONFIG_WILDFIREMOD)
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MCF5282_GPIO_DDRQS |= SPI_CS_MASK;
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MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK;
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#endif
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}
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if (command & QSPI_CS_ASSERT) {
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MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK;
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MCF5282_GPIO_PORTQS |= cs_mask;
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} else if (command & QSPI_CS_DROP) {
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MCF5282_GPIO_PORTQS |= SPI_CS_MASK;
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}
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}
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static int __init spi_dev_init(void)
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{
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int retval;
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retval = platform_device_register(&coldfire_spi);
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if (retval < 0)
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return retval;
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if (ARRAY_SIZE(spi_board_info))
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retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
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return retval;
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}
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#endif /* CONFIG_SPI */
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/***************************************************************************/
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