arm64: cpufeature: Add scope for capability check
Add scope parameter to the arm64_cpu_capabilities::matches(), so that this can be reused for checking the capability on a given CPU vs the system wide. The system uses the default scope associated with the capability for initialising the CPU_HWCAPs and ELF_HWCAPs. Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Родитель
9981293fb0
Коммит
92406f0cc9
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@ -78,10 +78,17 @@ struct arm64_ftr_reg {
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struct arm64_ftr_bits *ftr_bits;
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};
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/* scope of capability check */
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enum {
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SCOPE_SYSTEM,
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SCOPE_LOCAL_CPU,
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};
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struct arm64_cpu_capabilities {
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const char *desc;
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u16 capability;
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bool (*matches)(const struct arm64_cpu_capabilities *);
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int def_scope; /* default scope */
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bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
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void (*enable)(void *); /* Called on all active CPUs */
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union {
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struct { /* To be used for erratum handling only */
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@ -22,14 +22,16 @@
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#include <asm/cpufeature.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
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entry->midr_range_min,
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entry->midr_range_max);
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}
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#define MIDR_RANGE(model, min, max) \
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.def_scope = SCOPE_LOCAL_CPU, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = min, \
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@ -71,7 +71,8 @@ DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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/* meta feature for alternatives */
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static bool __maybe_unused
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cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
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cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
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static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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@ -626,6 +627,49 @@ u64 read_system_reg(u32 id)
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return regp->sys_val;
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}
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/*
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* __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
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* Read the system register on the current CPU
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*/
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static u64 __raw_read_system_reg(u32 sys_id)
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{
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switch (sys_id) {
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case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
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case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
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case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
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case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
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case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
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case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
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case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
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case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
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case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
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case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
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case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
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case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
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case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
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case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
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case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
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case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
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case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
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case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
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case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
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case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
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case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
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case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
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case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
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case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
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case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
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case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
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case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
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case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
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default:
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BUG();
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return 0;
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}
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}
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#include <linux/irqchip/arm-gic-v3.h>
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static bool
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@ -637,19 +681,24 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
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}
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static bool
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has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
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has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
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{
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u64 val;
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val = read_system_reg(entry->sys_reg);
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WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
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if (scope == SCOPE_SYSTEM)
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val = read_system_reg(entry->sys_reg);
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else
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val = __raw_read_system_reg(entry->sys_reg);
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return feature_matches(val, entry);
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}
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static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
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static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
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{
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bool has_sre;
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if (!has_cpuid_feature(entry))
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if (!has_cpuid_feature(entry, scope))
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return false;
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has_sre = gic_enable_sre();
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@ -660,7 +709,7 @@ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
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return has_sre;
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}
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static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
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static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
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{
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u32 midr = read_cpuid_id();
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u32 rv_min, rv_max;
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@ -672,7 +721,7 @@ static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
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return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
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}
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static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
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static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
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{
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return is_kernel_in_hyp_mode();
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}
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@ -681,6 +730,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "GIC system register CPU interface",
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.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
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.def_scope = SCOPE_SYSTEM,
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.matches = has_useable_gicv3_cpuif,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.field_pos = ID_AA64PFR0_GIC_SHIFT,
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@ -691,6 +741,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "Privileged Access Never",
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.capability = ARM64_HAS_PAN,
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.def_scope = SCOPE_SYSTEM,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64MMFR1_EL1,
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.field_pos = ID_AA64MMFR1_PAN_SHIFT,
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@ -703,6 +754,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "LSE atomic instructions",
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.capability = ARM64_HAS_LSE_ATOMICS,
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.def_scope = SCOPE_SYSTEM,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
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@ -713,12 +765,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "Software prefetching using PRFM",
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.capability = ARM64_HAS_NO_HW_PREFETCH,
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.def_scope = SCOPE_SYSTEM,
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.matches = has_no_hw_prefetch,
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},
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#ifdef CONFIG_ARM64_UAO
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{
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.desc = "User Access Override",
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.capability = ARM64_HAS_UAO,
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.def_scope = SCOPE_SYSTEM,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64MMFR2_EL1,
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.field_pos = ID_AA64MMFR2_UAO_SHIFT,
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@ -729,17 +783,20 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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#ifdef CONFIG_ARM64_PAN
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{
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.capability = ARM64_ALT_PAN_NOT_UAO,
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.def_scope = SCOPE_SYSTEM,
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.matches = cpufeature_pan_not_uao,
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},
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#endif /* CONFIG_ARM64_PAN */
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{
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.desc = "Virtualization Host Extensions",
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.capability = ARM64_HAS_VIRT_HOST_EXTN,
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.def_scope = SCOPE_SYSTEM,
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.matches = runs_at_el2,
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},
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{
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.desc = "32-bit EL0 Support",
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.capability = ARM64_HAS_32BIT_EL0,
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.def_scope = SCOPE_SYSTEM,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sign = FTR_UNSIGNED,
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@ -752,6 +809,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
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{ \
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.desc = #cap, \
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.def_scope = SCOPE_SYSTEM, \
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.matches = has_cpuid_feature, \
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.sys_reg = reg, \
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.field_pos = field, \
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@ -834,7 +892,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
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static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
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{
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for (; hwcaps->matches; hwcaps++)
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if (hwcaps->matches(hwcaps))
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if (hwcaps->matches(hwcaps, hwcaps->def_scope))
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cap_set_elf_hwcap(hwcaps);
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}
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@ -842,7 +900,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
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const char *info)
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{
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for (; caps->matches; caps++) {
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if (!caps->matches(caps))
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if (!caps->matches(caps, caps->def_scope))
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continue;
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if (!cpus_have_cap(caps->capability) && caps->desc)
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@ -878,48 +936,6 @@ static inline void set_sys_caps_initialised(void)
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sys_caps_initialised = true;
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}
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/*
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* __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
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*/
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static u64 __raw_read_system_reg(u32 sys_id)
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{
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switch (sys_id) {
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case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
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case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
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case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
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case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
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case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
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case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
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case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
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case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
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case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
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case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
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case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
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case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
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case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
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case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
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case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
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case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
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case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
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case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
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case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
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case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
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case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
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case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
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case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
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case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
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case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
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case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
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case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
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case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
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default:
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BUG();
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return 0;
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}
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}
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/*
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* Check for CPU features that are used in early boot
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* based on the Boot CPU value.
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@ -934,28 +950,25 @@ static void
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verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
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{
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for (; caps->matches; caps++) {
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if (!cpus_have_elf_hwcap(caps))
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continue;
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if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
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for (; caps->matches; caps++)
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if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
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pr_crit("CPU%d: missing HWCAP: %s\n",
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smp_processor_id(), caps->desc);
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cpu_die_early();
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}
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}
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}
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static void
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verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
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{
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for (; caps->matches; caps++) {
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if (!cpus_have_cap(caps->capability) || !caps->sys_reg)
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if (!cpus_have_cap(caps->capability))
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continue;
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/*
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* If the new CPU misses an advertised feature, we cannot proceed
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* further, park the cpu.
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*/
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if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
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if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
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pr_crit("CPU%d: missing feature: %s\n",
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smp_processor_id(), caps->desc);
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cpu_die_early();
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@ -1026,7 +1039,7 @@ void __init setup_cpu_features(void)
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}
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static bool __maybe_unused
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cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
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cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
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{
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return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
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}
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