drm/i915/skl: Implement WaSetGAPSunitClckGateDisable
Let's also take the opportunity the remove the comment telling it's a pre-prod W/A, it should be obvious from the stepping test. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -6018,6 +6018,7 @@ enum skl_disp_power_wells {
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#define GEN6_RSTCTL 0x9420
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#define GEN8_UCGCTL6 0x9430
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#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
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#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
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#define GEN6_GFXPAUSE 0xA000
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@ -59,9 +59,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
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if (INTEL_REVID(dev) == SKL_REVID_A0) {
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/*
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* WaDisableSDEUnitClockGating:skl
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* This seems to be a pre-production w/a.
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* WaSetGAPSunitClckGateDisable:skl
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*/
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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}
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}
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