phy: bcm-sr-pcie: Add Stingray PCIe PHY driver
Add Stingray PCIe PHY driver for both PAXB and PAXC root complex Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
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Коммит
92696a89cd
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@ -80,3 +80,13 @@ config PHY_BRCM_USB
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This driver is required by the USB XHCI, EHCI and OHCI
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drivers.
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If unsure, say N.
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config PHY_BCM_SR_PCIE
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tristate "Broadcom Stingray PCIe PHY driver"
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depends on OF && (ARCH_BCM_IPROC || COMPILE_TEST)
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select GENERIC_PHY
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select MFD_SYSCON
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default ARCH_BCM_IPROC
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help
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Enable this to support the Broadcom Stingray PCIe PHY
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If unsure, say N.
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@ -9,3 +9,5 @@ obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
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obj-$(CONFIG_PHY_BRCM_USB) += phy-brcm-usb-dvr.o
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phy-brcm-usb-dvr-objs := phy-brcm-usb.o phy-brcm-usb-init.o
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obj-$(CONFIG_PHY_BCM_SR_PCIE) += phy-bcm-sr-pcie.o
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@ -0,0 +1,305 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Broadcom
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/* we have up to 8 PAXB based RC. The 9th one is always PAXC */
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#define SR_NR_PCIE_PHYS 9
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#define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
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#define PCIE_PIPEMUX_CFG_OFFSET 0x10c
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#define PCIE_PIPEMUX_SELECT_STRAP 0xf
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#define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
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#define PCIE_PIPEMUX_SHIFT 19
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#define PCIE_PIPEMUX_MASK 0xf
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#define MHB_MEM_PW_PAXC_OFFSET 0x1c0
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#define MHB_PWR_ARR_POWERON 0x8
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#define MHB_PWR_ARR_POWEROK 0x4
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#define MHB_PWR_POWERON 0x2
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#define MHB_PWR_POWEROK 0x1
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#define MHB_PWR_STATUS_MASK (MHB_PWR_ARR_POWERON | \
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MHB_PWR_ARR_POWEROK | \
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MHB_PWR_POWERON | \
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MHB_PWR_POWEROK)
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struct sr_pcie_phy_core;
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/**
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* struct sr_pcie_phy - Stingray PCIe PHY
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*
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* @core: pointer to the Stingray PCIe PHY core control
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* @index: PHY index
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* @phy: pointer to the kernel PHY device
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*/
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struct sr_pcie_phy {
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struct sr_pcie_phy_core *core;
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unsigned int index;
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struct phy *phy;
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};
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/**
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* struct sr_pcie_phy_core - Stingray PCIe PHY core control
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*
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* @dev: pointer to device
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* @base: base register of PCIe SS
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* @cdru: regmap to the CDRU device
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* @mhb: regmap to the MHB device
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* @pipemux: pipemuex strap
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* @phys: array of PCIe PHYs
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*/
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struct sr_pcie_phy_core {
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struct device *dev;
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void __iomem *base;
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struct regmap *cdru;
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struct regmap *mhb;
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u32 pipemux;
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struct sr_pcie_phy phys[SR_NR_PCIE_PHYS];
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};
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/*
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* PCIe PIPEMUX lookup table
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*
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* Each array index represents a PIPEMUX strap setting
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* The array element represents a bitmap where a set bit means the PCIe
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* core and associated serdes has been enabled as RC and is available for use
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*/
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static const u8 pipemux_table[] = {
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/* PIPEMUX = 0, EP 1x16 */
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0x00,
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/* PIPEMUX = 1, EP 2x8 */
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0x00,
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/* PIPEMUX = 2, EP 4x4 */
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0x00,
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/* PIPEMUX = 3, RC 2x8, cores 0, 7 */
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0x81,
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/* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
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0xc3,
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/* PIPEMUX = 5, RC 8x2, all 8 cores */
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0xff,
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/* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
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0xcd,
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/* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
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0xfd,
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/* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
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0xf0,
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/* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
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0xc0,
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/* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
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0x42,
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/* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
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0x3c,
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/* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
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0xfc,
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/* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
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0x4c,
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};
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/*
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* Return true if the strap setting is valid
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*/
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static bool pipemux_strap_is_valid(u32 pipemux)
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{
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return !!(pipemux < ARRAY_SIZE(pipemux_table));
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}
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/*
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* Read the PCIe PIPEMUX from strap
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*/
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static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
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{
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u32 pipemux;
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/*
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* Read PIPEMUX configuration register to determine the pipemux setting
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*
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* In the case when the value indicates using HW strap, fall back to
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* use HW strap
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*/
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pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
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pipemux &= PCIE_PIPEMUX_MASK;
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if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
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regmap_read(core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, &pipemux);
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pipemux >>= PCIE_PIPEMUX_SHIFT;
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pipemux &= PCIE_PIPEMUX_MASK;
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}
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return pipemux;
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}
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/*
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* Given a PIPEMUX strap and PCIe core index, this function returns true if the
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* PCIe core needs to be enabled
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*/
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static bool pcie_core_is_for_rc(struct sr_pcie_phy *phy)
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{
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struct sr_pcie_phy_core *core = phy->core;
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unsigned int core_idx = phy->index;
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return !!((pipemux_table[core->pipemux] >> core_idx) & 0x1);
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}
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static int sr_pcie_phy_init(struct phy *p)
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{
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struct sr_pcie_phy *phy = phy_get_drvdata(p);
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/*
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* Check whether this PHY is for root complex or not. If yes, return
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* zero so the host driver can proceed to enumeration. If not, return
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* an error and that will force the host driver to bail out
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*/
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if (pcie_core_is_for_rc(phy))
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return 0;
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return -ENODEV;
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}
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static int sr_paxc_phy_init(struct phy *p)
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{
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struct sr_pcie_phy *phy = phy_get_drvdata(p);
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struct sr_pcie_phy_core *core = phy->core;
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unsigned int core_idx = phy->index;
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u32 val;
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if (core_idx != SR_PAXC_PHY_IDX)
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return -EINVAL;
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regmap_read(core->mhb, MHB_MEM_PW_PAXC_OFFSET, &val);
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if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) {
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dev_err(core->dev, "PAXC is not powered up\n");
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return -ENODEV;
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}
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return 0;
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}
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static const struct phy_ops sr_pcie_phy_ops = {
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.init = sr_pcie_phy_init,
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.owner = THIS_MODULE,
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};
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static const struct phy_ops sr_paxc_phy_ops = {
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.init = sr_paxc_phy_init,
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.owner = THIS_MODULE,
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};
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static struct phy *sr_pcie_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct sr_pcie_phy_core *core;
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int phy_idx;
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core = dev_get_drvdata(dev);
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if (!core)
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return ERR_PTR(-EINVAL);
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phy_idx = args->args[0];
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if (WARN_ON(phy_idx >= SR_NR_PCIE_PHYS))
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return ERR_PTR(-ENODEV);
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return core->phys[phy_idx].phy;
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}
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static int sr_pcie_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct sr_pcie_phy_core *core;
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struct resource *res;
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struct phy_provider *provider;
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unsigned int phy_idx = 0;
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core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
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if (!core)
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return -ENOMEM;
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core->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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core->base = devm_ioremap_resource(core->dev, res);
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if (IS_ERR(core->base))
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return PTR_ERR(core->base);
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core->cdru = syscon_regmap_lookup_by_phandle(node, "brcm,sr-cdru");
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if (IS_ERR(core->cdru)) {
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dev_err(core->dev, "unable to find CDRU device\n");
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return PTR_ERR(core->cdru);
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}
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core->mhb = syscon_regmap_lookup_by_phandle(node, "brcm,sr-mhb");
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if (IS_ERR(core->mhb)) {
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dev_err(core->dev, "unable to find MHB device\n");
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return PTR_ERR(core->mhb);
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}
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/* read the PCIe PIPEMUX strap setting */
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core->pipemux = pipemux_strap_read(core);
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if (!pipemux_strap_is_valid(core->pipemux)) {
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dev_err(core->dev, "invalid PCIe PIPEMUX strap %u\n",
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core->pipemux);
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return -EIO;
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}
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for (phy_idx = 0; phy_idx < SR_NR_PCIE_PHYS; phy_idx++) {
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struct sr_pcie_phy *p = &core->phys[phy_idx];
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const struct phy_ops *ops;
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if (phy_idx == SR_PAXC_PHY_IDX)
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ops = &sr_paxc_phy_ops;
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else
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ops = &sr_pcie_phy_ops;
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p->phy = devm_phy_create(dev, NULL, ops);
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if (IS_ERR(p->phy)) {
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dev_err(dev, "failed to create PCIe PHY\n");
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return PTR_ERR(p->phy);
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}
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p->core = core;
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p->index = phy_idx;
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phy_set_drvdata(p->phy, p);
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}
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dev_set_drvdata(dev, core);
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provider = devm_of_phy_provider_register(dev, sr_pcie_phy_xlate);
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if (IS_ERR(provider)) {
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dev_err(dev, "failed to register PHY provider\n");
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return PTR_ERR(provider);
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}
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dev_info(dev, "Stingray PCIe PHY driver initialized\n");
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return 0;
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}
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static const struct of_device_id sr_pcie_phy_match_table[] = {
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{ .compatible = "brcm,sr-pcie-phy" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sr_pcie_phy_match_table);
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static struct platform_driver sr_pcie_phy_driver = {
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.driver = {
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.name = "sr-pcie-phy",
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.of_match_table = sr_pcie_phy_match_table,
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},
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.probe = sr_pcie_phy_probe,
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};
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module_platform_driver(sr_pcie_phy_driver);
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MODULE_AUTHOR("Ray Jui <ray.jui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom Stingray PCIe PHY driver");
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MODULE_LICENSE("GPL v2");
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