net/mlx5e: Wake On LAN support
Implement set/get WOL by ethtool and added the needed device commands and structures to mlx5_ifc. Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Rana Shahout <ranas@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tariq Toukan
David S. Miller
Родитель
d8880795da
Коммит
928cfe8745
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@ -560,6 +560,12 @@ const char *mlx5_command_str(int command)
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case MLX5_CMD_OP_ACCESS_REG:
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return "MLX5_CMD_OP_ACCESS_REG";
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case MLX5_CMD_OP_SET_WOL_ROL:
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return "SET_WOL_ROL";
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case MLX5_CMD_OP_QUERY_WOL_ROL:
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return "QUERY_WOL_ROL";
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default: return "unknown command opcode";
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}
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}
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@ -884,6 +884,129 @@ static int mlx5e_get_ts_info(struct net_device *dev,
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return 0;
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}
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static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
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{
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__u32 ret = 0;
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if (MLX5_CAP_GEN(mdev, wol_g))
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ret |= WAKE_MAGIC;
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if (MLX5_CAP_GEN(mdev, wol_s))
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ret |= WAKE_MAGICSECURE;
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if (MLX5_CAP_GEN(mdev, wol_a))
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ret |= WAKE_ARP;
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if (MLX5_CAP_GEN(mdev, wol_b))
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ret |= WAKE_BCAST;
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if (MLX5_CAP_GEN(mdev, wol_m))
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ret |= WAKE_MCAST;
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if (MLX5_CAP_GEN(mdev, wol_u))
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ret |= WAKE_UCAST;
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if (MLX5_CAP_GEN(mdev, wol_p))
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ret |= WAKE_PHY;
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return ret;
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}
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static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
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{
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__u32 ret = 0;
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if (mode & MLX5_WOL_MAGIC)
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ret |= WAKE_MAGIC;
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if (mode & MLX5_WOL_SECURED_MAGIC)
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ret |= WAKE_MAGICSECURE;
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if (mode & MLX5_WOL_ARP)
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ret |= WAKE_ARP;
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if (mode & MLX5_WOL_BROADCAST)
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ret |= WAKE_BCAST;
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if (mode & MLX5_WOL_MULTICAST)
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ret |= WAKE_MCAST;
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if (mode & MLX5_WOL_UNICAST)
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ret |= WAKE_UCAST;
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if (mode & MLX5_WOL_PHY_ACTIVITY)
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ret |= WAKE_PHY;
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return ret;
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}
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static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
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{
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u8 ret = 0;
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if (mode & WAKE_MAGIC)
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ret |= MLX5_WOL_MAGIC;
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if (mode & WAKE_MAGICSECURE)
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ret |= MLX5_WOL_SECURED_MAGIC;
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if (mode & WAKE_ARP)
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ret |= MLX5_WOL_ARP;
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if (mode & WAKE_BCAST)
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ret |= MLX5_WOL_BROADCAST;
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if (mode & WAKE_MCAST)
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ret |= MLX5_WOL_MULTICAST;
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if (mode & WAKE_UCAST)
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ret |= MLX5_WOL_UNICAST;
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if (mode & WAKE_PHY)
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ret |= MLX5_WOL_PHY_ACTIVITY;
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return ret;
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}
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static void mlx5e_get_wol(struct net_device *netdev,
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struct ethtool_wolinfo *wol)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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u8 mlx5_wol_mode;
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int err;
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memset(wol, 0, sizeof(*wol));
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wol->supported = mlx5e_get_wol_supported(mdev);
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if (!wol->supported)
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return;
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err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
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if (err)
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return;
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wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
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}
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static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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__u32 wol_supported = mlx5e_get_wol_supported(mdev);
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u32 mlx5_wol_mode;
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if (!wol_supported)
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return -ENOTSUPP;
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if (wol->wolopts & ~wol_supported)
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return -EINVAL;
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mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
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return mlx5_set_port_wol(mdev, mlx5_wol_mode);
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}
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const struct ethtool_ops mlx5e_ethtool_ops = {
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.get_drvinfo = mlx5e_get_drvinfo,
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.get_link = ethtool_op_get_link,
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@ -908,4 +1031,6 @@ const struct ethtool_ops mlx5e_ethtool_ops = {
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.get_pauseparam = mlx5e_get_pauseparam,
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.set_pauseparam = mlx5e_set_pauseparam,
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.get_ts_info = mlx5e_get_ts_info,
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.get_wol = mlx5e_get_wol,
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.set_wol = mlx5e_set_wol,
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};
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@ -546,3 +546,41 @@ int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
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return 0;
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
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int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
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{
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u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
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u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
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memset(in, 0, sizeof(in));
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memset(out, 0, sizeof(out));
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MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
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MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
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MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
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return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
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out, sizeof(out));
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
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int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
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{
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u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
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u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
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int err;
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memset(in, 0, sizeof(in));
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memset(out, 0, sizeof(out));
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MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
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err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
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out, sizeof(out));
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if (!err)
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*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
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@ -1183,6 +1183,17 @@ enum {
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MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
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};
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enum mlx5_wol_mode {
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MLX5_WOL_DISABLE = 0,
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MLX5_WOL_SECURED_MAGIC = 1 << 1,
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MLX5_WOL_MAGIC = 1 << 2,
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MLX5_WOL_ARP = 1 << 3,
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MLX5_WOL_BROADCAST = 1 << 4,
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MLX5_WOL_MULTICAST = 1 << 5,
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MLX5_WOL_UNICAST = 1 << 6,
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MLX5_WOL_PHY_ACTIVITY = 1 << 7,
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};
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/* MLX5 DEV CAPs */
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/* TODO: EAT.ME */
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@ -166,6 +166,8 @@ enum {
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MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
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MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
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MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
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MLX5_CMD_OP_SET_WOL_ROL = 0x830,
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MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
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MLX5_CMD_OP_CREATE_TIR = 0x900,
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MLX5_CMD_OP_MODIFY_TIR = 0x901,
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MLX5_CMD_OP_DESTROY_TIR = 0x902,
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@ -731,7 +733,17 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 log_max_msg[0x5];
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u8 reserved_at_1c7[0x4];
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u8 max_tc[0x4];
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u8 reserved_at_1cf[0x10];
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u8 reserved_at_1cf[0x6];
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u8 rol_s[0x1];
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u8 rol_g[0x1];
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u8 reserved_at_1d7[0x1];
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u8 wol_s[0x1];
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u8 wol_g[0x1];
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u8 wol_a[0x1];
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u8 wol_b[0x1];
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u8 wol_m[0x1];
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u8 wol_u[0x1];
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u8 wol_p[0x1];
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u8 stat_rate_support[0x10];
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u8 reserved_at_1ef[0xc];
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@ -6873,6 +6885,54 @@ struct mlx5_ifc_mtt_bits {
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u8 rd_en[0x1];
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};
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struct mlx5_ifc_query_wol_rol_out_bits {
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u8 status[0x8];
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u8 reserved_at_8[0x18];
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u8 syndrome[0x20];
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u8 reserved_at_40[0x10];
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u8 rol_mode[0x8];
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u8 wol_mode[0x8];
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u8 reserved_at_60[0x20];
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};
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struct mlx5_ifc_query_wol_rol_in_bits {
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u8 opcode[0x10];
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u8 reserved_at_10[0x10];
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u8 reserved_at_20[0x10];
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u8 op_mod[0x10];
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u8 reserved_at_40[0x40];
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};
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struct mlx5_ifc_set_wol_rol_out_bits {
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u8 status[0x8];
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u8 reserved_at_8[0x18];
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u8 syndrome[0x20];
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u8 reserved_at_40[0x40];
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};
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struct mlx5_ifc_set_wol_rol_in_bits {
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u8 opcode[0x10];
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u8 reserved_at_10[0x10];
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u8 reserved_at_20[0x10];
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u8 op_mod[0x10];
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u8 rol_mode_valid[0x1];
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u8 wol_mode_valid[0x1];
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u8 reserved_at_42[0xe];
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u8 rol_mode[0x8];
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u8 wol_mode[0x8];
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u8 reserved_at_60[0x20];
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};
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enum {
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MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
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MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
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@ -81,5 +81,7 @@ int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
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int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
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u8 *max_bw_value,
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u8 *max_bw_unit);
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int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
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int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
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#endif /* __MLX5_PORT_H__ */
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