drm/amdgpu/vcn:Update SPG mode VCN global tiling
Update Static Power Gate mode VCN global tiling Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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92bbdaeb91
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@ -325,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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}
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static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
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