From d9c26e0a58b0039d1ad4340d826fe8db866e9455 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Wed, 8 Jun 2022 22:40:55 +0800 Subject: [PATCH 1/6] mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb rx_callback is a standard mailbox callback mechanism and could cover the function of proprietary cmdq_task_cb, so use the standard one instead of the proprietary one. Client driver has changed to use standard rx_callback, so remove proprietary cmdq_task_cb. Signed-off-by: Chun-Kuang Hu Reviewed-by: Matthias Brugger Signed-off-by: Jassi Brar --- drivers/mailbox/mtk-cmdq-mailbox.c | 11 ----------- include/linux/mailbox/mtk-cmdq-mailbox.h | 10 ---------- 2 files changed, 21 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 2578e5aaa935..9465f9081515 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -192,15 +192,10 @@ static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) static void cmdq_task_exec_done(struct cmdq_task *task, int sta) { - struct cmdq_task_cb *cb = &task->pkt->async_cb; struct cmdq_cb_data data; data.sta = sta; - data.data = cb->data; data.pkt = task->pkt; - if (cb->cb) - cb->cb(data); - mbox_chan_received_data(task->thread->chan, &data); list_del(&task->list_entry); @@ -448,7 +443,6 @@ done: static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) { struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; - struct cmdq_task_cb *cb; struct cmdq_cb_data data; struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); struct cmdq_task *task, *tmp; @@ -465,13 +459,8 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) list_for_each_entry_safe(task, tmp, &thread->task_busy_list, list_entry) { - cb = &task->pkt->async_cb; data.sta = -ECONNABORTED; - data.data = cb->data; data.pkt = task->pkt; - if (cb->cb) - cb->cb(data); - mbox_chan_received_data(task->thread->chan, &data); list_del(&task->list_entry); kfree(task); diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index 44365aab043c..a8f0070c7aa9 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -67,24 +67,14 @@ enum cmdq_code { struct cmdq_cb_data { int sta; - void *data; struct cmdq_pkt *pkt; }; -typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data); - -struct cmdq_task_cb { - cmdq_async_flush_cb cb; - void *data; -}; - struct cmdq_pkt { void *va_base; dma_addr_t pa_base; size_t cmd_buf_size; /* command occupied size */ size_t buf_size; /* real buffer size */ - struct cmdq_task_cb cb; - struct cmdq_task_cb async_cb; void *cl; }; From 60545466180e791827c84795e7b4828dbeb9e061 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 18 Jul 2022 12:55:38 +0100 Subject: [PATCH 2/6] dt-bindings: mailbox: qcom,apcs-kpss-global: Add syscon const for relevant entries msm8916, msm8939, msm8953, msm8994 and qcs404 already declare or should declare syscon as they have drivers that use syscon inside of the apcs-kpss block. grep apcs arch/arm64/boot/dts/qcom/* | grep syscon Add in the additional syscon in the documentation for the above mentioned parts. Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue Signed-off-by: Jassi Brar --- .../mailbox/qcom,apcs-kpss-global.yaml | 46 ++++++++++--------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 3b5ba7ecc19d..f504652fc0ea 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -15,26 +15,30 @@ maintainers: properties: compatible: - enum: - - qcom,ipq6018-apcs-apps-global - - qcom,ipq8074-apcs-apps-global - - qcom,msm8916-apcs-kpss-global - - qcom,msm8939-apcs-kpss-global - - qcom,msm8953-apcs-kpss-global - - qcom,msm8976-apcs-kpss-global - - qcom,msm8994-apcs-kpss-global - - qcom,msm8996-apcs-hmss-global - - qcom,msm8998-apcs-hmss-global - - qcom,qcm2290-apcs-hmss-global - - qcom,qcs404-apcs-apps-global - - qcom,sc7180-apss-shared - - qcom,sc8180x-apss-shared - - qcom,sdm660-apcs-hmss-global - - qcom,sdm845-apss-shared - - qcom,sm6125-apcs-hmss-global - - qcom,sm6115-apcs-hmss-global - - qcom,sm8150-apss-shared - + oneOf: + - items: + - enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + - qcom,msm8976-apcs-kpss-global + - qcom,msm8996-apcs-hmss-global + - qcom,msm8998-apcs-hmss-global + - qcom,qcm2290-apcs-hmss-global + - qcom,sc7180-apss-shared + - qcom,sc8180x-apss-shared + - qcom,sdm660-apcs-hmss-global + - qcom,sdm845-apss-shared + - qcom,sm6125-apcs-hmss-global + - qcom,sm6115-apcs-hmss-global + - qcom,sm8150-apss-shared + - items: + - enum: + - qcom,msm8916-apcs-kpss-global + - qcom,msm8939-apcs-kpss-global + - qcom,msm8953-apcs-kpss-global + - qcom,msm8994-apcs-kpss-global + - qcom,qcs404-apcs-apps-global + - const: syscon reg: maxItems: 1 @@ -121,7 +125,7 @@ examples: #define GCC_APSS_AHB_CLK_SRC 1 #define GCC_GPLL0_AO_OUT_MAIN 123 apcs: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global"; + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; From 095730dd4ca5fe078fd07db5be68b3026d4ae48a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 15 Jun 2022 21:00:08 +0800 Subject: [PATCH 3/6] dt-bindings: mailbox: imx-mu: add RST channel i.MX MU has a MUR bit which is to reset both the Processor B and the Processor A sides of the MU module, forcing all control and status registers to return to their default values (except the BHR bit in the ACR register and BHRM bit in BCR register), and all internal states to be cleared. Signed-off-by: Peng Fan Reviewed-by: Rob Herring Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index 7a86e7926dd2..191c1ce15009 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -72,14 +72,16 @@ properties: type : Channel type channel : Channel number - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are + This MU support 5 type of unidirectional channels, each type + has 4 channels except RST channel which only has 1 channel. + A total of 17 channels. Following types are supported: 0 - TX channel with 32bit transmit register and IRQ transmit acknowledgment support. 1 - RX channel with 32bit receive register and IRQ support 2 - TX doorbell channel. Without own register and no ACK support. 3 - RX doorbell channel. + 4 - RST channel const: 2 clocks: From 82ab513baed5895c8b0e991557a12fd38d5f25f0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 15 Jun 2022 21:00:09 +0800 Subject: [PATCH 4/6] mailbox: imx: support RST channel i.MX generic MU supports MU-A/B reset feature. When stop/start remotecore, MU is not reset. So when Linux stop remotecore, the MU-B side BCR may contain valid configuration, because MU-B is not reset. So when linux start Mcore again and notify Mcore, Mcore is not ready to handle MU interrupt and cause issues. So need reset MU when stop Mcore. Signed-off-by: Peng Fan Signed-off-by: Jassi Brar --- drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index b10239d6ef93..37fc765783f8 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -19,7 +19,7 @@ #include #include -#define IMX_MU_CHANS 16 +#define IMX_MU_CHANS 17 /* TX0/RX0/RXDB[0-3] */ #define IMX_MU_SCU_CHANS 6 /* TX0/RX0 */ @@ -35,9 +35,11 @@ enum imx_mu_chan_type { IMX_MU_TYPE_RX = 1, /* Rx */ IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ + IMX_MU_TYPE_RST = 4, /* Reset */ }; enum imx_mu_xcr { + IMX_MU_CR, IMX_MU_GIER, IMX_MU_GCR, IMX_MU_TCR, @@ -50,6 +52,7 @@ enum imx_mu_xsr { IMX_MU_GSR, IMX_MU_TSR, IMX_MU_RSR, + IMX_MU_xSR_MAX, }; struct imx_sc_rpc_msg_max { @@ -85,7 +88,7 @@ struct imx_mu_priv { int irq[IMX_MU_CHANS]; bool suspend; - u32 xcr[4]; + u32 xcr[IMX_MU_xCR_MAX]; bool side_b; }; @@ -105,8 +108,8 @@ struct imx_mu_dcfg { enum imx_mu_type type; u32 xTR; /* Transmit Register0 */ u32 xRR; /* Receive Register0 */ - u32 xSR[4]; /* Status Registers */ - u32 xCR[4]; /* Control Registers */ + u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ + u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ }; #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) @@ -121,6 +124,9 @@ struct imx_mu_dcfg { #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) /* General Purpose Interrupt Request */ #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) +/* MU reset */ +#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) +#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) @@ -497,6 +503,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); break; + case IMX_MU_TYPE_RST: + return IRQ_NONE; default: dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", cp->type); @@ -581,6 +589,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan) { struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; + int ret; + u32 sr; if (cp->type == IMX_MU_TYPE_TXDB) { tasklet_kill(&cp->txdb_tasklet); @@ -598,6 +608,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan) case IMX_MU_TYPE_RXDB: imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); break; + case IMX_MU_TYPE_RST: + imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); + ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, + !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); + if (ret) + dev_warn(priv->dev, "RST channel timeout\n"); + break; default: break; } @@ -865,7 +882,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { .xTR = 0x0, .xRR = 0x10, .xSR = {0x20, 0x20, 0x20, 0x20}, - .xCR = {0x24, 0x24, 0x24, 0x24}, + .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, }; static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { @@ -888,7 +905,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .xTR = 0x200, .xRR = 0x280, .xSR = {0xC, 0x118, 0x124, 0x12C}, - .xCR = {0x110, 0x114, 0x120, 0x128}, + .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, }; static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { From 1a607e102fe0f04491fb69c5a233aad139d9d1d6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 16 Jul 2022 21:32:56 +0200 Subject: [PATCH 5/6] dt-bindings: mailbox: qcom-ipcc: Add SM6375 compatible Add a compatible for SM6375. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index 1994be858940..baca4786ff94 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - qcom,sm6350-ipcc + - qcom,sm6375-ipcc - qcom,sm8250-ipcc - qcom,sm8350-ipcc - qcom,sm8450-ipcc From 8a8dc2b9596e6088522d30bc79306b834c681943 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 3 Aug 2022 15:53:26 +0800 Subject: [PATCH 6/6] mailbox: imx: clear pending interrupts During MU initialization, there maybe pending GSR and RSR pending interrupt, clear them to avoid unexpected kernel dump when requesting mailbox channel Reviewed-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan Signed-off-by: Jassi Brar --- drivers/mailbox/imx-mailbox.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 37fc765783f8..02922073c9ef 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -26,6 +26,8 @@ #define IMX_MU_S4_CHANS 2 #define IMX_MU_CHAN_NAME_SIZE 20 +#define IMX_MU_NUM_RR 4 + #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) @@ -711,6 +713,7 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, static void imx_mu_init_generic(struct imx_mu_priv *priv) { unsigned int i; + unsigned int val; for (i = 0; i < IMX_MU_CHANS; i++) { struct imx_mu_con_priv *cp = &priv->con_priv[i]; @@ -732,6 +735,14 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) /* Set default MU configuration */ for (i = 0; i < IMX_MU_xCR_MAX; i++) imx_mu_write(priv, 0, priv->dcfg->xCR[i]); + + /* Clear any pending GIP */ + val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); + imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); + + /* Clear any pending RSR */ + for (i = 0; i < IMX_MU_NUM_RR; i++) + imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); } static void imx_mu_init_specific(struct imx_mu_priv *priv)