ASoC: Intel: Bxtn: Add Broxton DSP support
Broxton DSP is mostly similar to Skylake one but with subtle differences like no Code Load DMA and uses HDA DMA for code loading, DSP D0 and D3 sequences are different. These changes are comprehended by adding different DSP power up and down handlers, and new loader ops and also adding prepare and trigger which HDA DSP DMA requires Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Jayachandran B <jayachandran.b@intel.com> Signed-off-by: GuruprasadX Pawse <guruprasadx.pawse@intel.com> Signed-off-by: Kranthi G <gudishax.kranthikumar@intel.com> Signed-off-by: Dharageswari R <dharageswari.r@intel.com> Signed-off-by: Ramesh Babu <ramesh.babu@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jeeja KP
Mark Brown
Родитель
f17131a93f
Коммит
92eb4f62cb
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@ -162,6 +162,7 @@ config SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH
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config SND_SOC_INTEL_SKYLAKE
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tristate
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select SND_HDA_EXT_CORE
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select SND_HDA_DSP_LOADER
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select SND_SOC_TOPOLOGY
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select SND_HDA_I915
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select SND_SOC_INTEL_SST
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@ -5,6 +5,6 @@ obj-$(CONFIG_SND_SOC_INTEL_SKYLAKE) += snd-soc-skl.o
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# Skylake IPC Support
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snd-soc-skl-ipc-objs := skl-sst-ipc.o skl-sst-dsp.o skl-sst-cldma.o \
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skl-sst.o
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skl-sst.o bxt-sst.o
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obj-$(CONFIG_SND_SOC_INTEL_SKYLAKE) += snd-soc-skl-ipc.o
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@ -0,0 +1,328 @@
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/*
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* bxt-sst.c - DSP library functions for BXT platform
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*
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* Copyright (C) 2015-16 Intel Corp
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* Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
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* Jeeja KP <jeeja.kp@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/device.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-dsp-priv.h"
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#include "skl-sst-ipc.h"
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#define BXT_BASEFW_TIMEOUT 3000
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#define BXT_INIT_TIMEOUT 500
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#define BXT_IPC_PURGE_FW 0x01004000
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#define BXT_ROM_INIT 0x5
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#define BXT_ADSP_SRAM0_BASE 0x80000
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/* Firmware status window */
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#define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
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#define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
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#define BXT_ADSP_SRAM1_BASE 0xA0000
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static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
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}
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static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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const void *fwdata, u32 fwsize)
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{
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int stream_tag, ret, i;
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u32 reg;
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stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
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if (stream_tag < 0) {
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dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
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stream_tag);
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return stream_tag;
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}
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ctx->dsp_ops.stream_tag = stream_tag;
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memcpy(ctx->dmab.area, fwdata, fwsize);
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/* Purge FW request */
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
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BXT_IPC_PURGE_FW | (stream_tag - 1));
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ret = skl_dsp_enable_core(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
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ret = -EIO;
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goto base_fw_load_failed;
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}
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for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
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reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
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if (reg & SKL_ADSP_REG_HIPCIE_DONE) {
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sst_dsp_shim_update_bits_forced(ctx,
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SKL_ADSP_REG_HIPCIE,
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SKL_ADSP_REG_HIPCIE_DONE,
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SKL_ADSP_REG_HIPCIE_DONE);
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break;
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}
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mdelay(1);
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}
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if (!i) {
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dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg);
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE,
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SKL_ADSP_REG_HIPCIE_DONE,
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SKL_ADSP_REG_HIPCIE_DONE);
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}
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/* enable Interrupt */
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
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if (SKL_FW_INIT ==
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(sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
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SKL_FW_STS_MASK)) {
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dev_info(ctx->dev, "ROM loaded, continue FW loading\n");
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break;
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}
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mdelay(1);
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}
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if (!i) {
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dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg);
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ret = -EIO;
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goto base_fw_load_failed;
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}
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return ret;
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base_fw_load_failed:
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ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
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skl_dsp_disable_core(ctx);
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return ret;
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}
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static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
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{
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int ret;
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ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
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ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
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BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
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ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
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ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
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return ret;
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}
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static int bxt_load_base_firmware(struct sst_dsp *ctx)
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{
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const struct firmware *fw = NULL;
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struct skl_sst *skl = ctx->thread_context;
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int ret;
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ret = request_firmware(&fw, ctx->fw_name, ctx->dev);
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if (ret < 0) {
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dev_err(ctx->dev, "Request firmware failed %d\n", ret);
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goto sst_load_base_firmware_failed;
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}
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ret = sst_bxt_prepare_fw(ctx, fw->data, fw->size);
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/* Retry Enabling core and ROM load. Retry seemed to help */
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if (ret < 0) {
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ret = sst_bxt_prepare_fw(ctx, fw->data, fw->size);
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if (ret < 0) {
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dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
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goto sst_load_base_firmware_failed;
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}
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}
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ret = sst_transfer_fw_host_dma(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
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dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
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sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
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sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
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skl_dsp_disable_core(ctx);
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} else {
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dev_dbg(ctx->dev, "Firmware download successful\n");
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ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
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skl_dsp_disable_core(ctx);
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ret = -EIO;
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} else {
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skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
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ret = 0;
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}
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}
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sst_load_base_firmware_failed:
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release_firmware(fw);
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return ret;
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}
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static int bxt_set_dsp_D0(struct sst_dsp *ctx)
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{
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struct skl_sst *skl = ctx->thread_context;
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int ret;
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skl->boot_complete = false;
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ret = skl_dsp_enable_core(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret);
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return ret;
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}
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/* enable interrupt */
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev, "ipc: error DSP boot timeout\n");
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dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
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sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
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sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
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return -EIO;
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}
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skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
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return 0;
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}
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static int bxt_set_dsp_D3(struct sst_dsp *ctx)
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{
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struct skl_ipc_dxstate_info dx;
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struct skl_sst *skl = ctx->thread_context;
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int ret = 0;
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if (!is_skl_dsp_running(ctx))
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return ret;
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dx.core_mask = SKL_DSP_CORE0_MASK;
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dx.dx_mask = SKL_IPC_D3_MASK;
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ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
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SKL_BASE_FW_MODULE_ID, &dx);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret);
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return ret;
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}
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ret = skl_dsp_disable_core(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret);
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ret = -EIO;
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}
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skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
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return 0;
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}
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static struct skl_dsp_fw_ops bxt_fw_ops = {
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.set_state_D0 = bxt_set_dsp_D0,
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.set_state_D3 = bxt_set_dsp_D3,
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.load_fw = bxt_load_base_firmware,
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.get_fw_errcode = bxt_get_errorcode,
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};
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static struct sst_ops skl_ops = {
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.irq_handler = skl_dsp_sst_interrupt,
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.write = sst_shim32_write,
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.read = sst_shim32_read,
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.ram_read = sst_memcpy_fromio_32,
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.ram_write = sst_memcpy_toio_32,
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.free = skl_dsp_free,
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};
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static struct sst_dsp_device skl_dev = {
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.thread = skl_dsp_irq_thread_handler,
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.ops = &skl_ops,
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};
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int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
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const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
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struct skl_sst **dsp)
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{
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struct skl_sst *skl;
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struct sst_dsp *sst;
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int ret;
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skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
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if (skl == NULL)
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return -ENOMEM;
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skl->dev = dev;
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skl_dev.thread_context = skl;
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skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
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if (!skl->dsp) {
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dev_err(skl->dev, "skl_dsp_ctx_init failed\n");
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return -ENODEV;
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}
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sst = skl->dsp;
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sst->fw_name = fw_name;
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sst->dsp_ops = dsp_ops;
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sst->fw_ops = bxt_fw_ops;
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sst->addr.lpe = mmio_base;
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sst->addr.shim = mmio_base;
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sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
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SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
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ret = skl_ipc_init(dev, skl);
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if (ret)
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return ret;
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skl->boot_complete = false;
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init_waitqueue_head(&skl->boot_wait);
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ret = sst->fw_ops.load_fw(sst);
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if (ret < 0) {
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dev_err(dev, "Load base fw failed: %x", ret);
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return ret;
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}
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if (dsp)
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*dsp = skl;
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return 0;
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}
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EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
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void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
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{
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skl_ipc_free(&ctx->ipc);
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ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
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if (ctx->dsp->addr.lpe)
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iounmap(ctx->dsp->addr.lpe);
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ctx->dsp->ops->free(ctx->dsp);
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}
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EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel Broxton IPC driver");
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@ -72,6 +72,105 @@ static void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable)
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skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)&mask);
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}
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static int skl_dsp_setup_spib(struct device *dev, unsigned int size,
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int stream_tag, int enable)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
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struct hdac_bus *bus = ebus_to_hbus(ebus);
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struct hdac_stream *stream = snd_hdac_get_stream(bus,
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SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
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struct hdac_ext_stream *estream;
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if (!stream)
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return -EINVAL;
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estream = stream_to_hdac_ext_stream(stream);
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/* enable/disable SPIB for this hdac stream */
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snd_hdac_ext_stream_spbcap_enable(ebus, enable, stream->index);
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/* set the spib value */
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snd_hdac_ext_stream_set_spib(ebus, estream, size);
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return 0;
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}
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static int skl_dsp_prepare(struct device *dev, unsigned int format,
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unsigned int size, struct snd_dma_buffer *dmab)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
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struct hdac_bus *bus = ebus_to_hbus(ebus);
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struct hdac_ext_stream *estream;
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struct hdac_stream *stream;
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struct snd_pcm_substream substream;
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int ret;
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if (!bus)
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return -ENODEV;
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memset(&substream, 0, sizeof(substream));
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substream.stream = SNDRV_PCM_STREAM_PLAYBACK;
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estream = snd_hdac_ext_stream_assign(ebus, &substream,
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HDAC_EXT_STREAM_TYPE_HOST);
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if (!estream)
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return -ENODEV;
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stream = hdac_stream(estream);
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/* assign decouple host dma channel */
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ret = snd_hdac_dsp_prepare(stream, format, size, dmab);
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if (ret < 0)
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return ret;
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skl_dsp_setup_spib(dev, size, stream->stream_tag, true);
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return stream->stream_tag;
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}
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static int skl_dsp_trigger(struct device *dev, bool start, int stream_tag)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
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struct hdac_stream *stream;
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struct hdac_bus *bus = ebus_to_hbus(ebus);
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if (!bus)
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return -ENODEV;
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stream = snd_hdac_get_stream(bus,
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SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
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if (!stream)
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return -EINVAL;
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snd_hdac_dsp_trigger(stream, start);
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return 0;
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||||
}
|
||||
|
||||
static int skl_dsp_cleanup(struct device *dev,
|
||||
struct snd_dma_buffer *dmab, int stream_tag)
|
||||
{
|
||||
struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
|
||||
struct hdac_stream *stream;
|
||||
struct hdac_ext_stream *estream;
|
||||
struct hdac_bus *bus = ebus_to_hbus(ebus);
|
||||
|
||||
if (!bus)
|
||||
return -ENODEV;
|
||||
|
||||
stream = snd_hdac_get_stream(bus,
|
||||
SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
|
||||
if (!stream)
|
||||
return -EINVAL;
|
||||
|
||||
estream = stream_to_hdac_ext_stream(stream);
|
||||
skl_dsp_setup_spib(dev, 0, stream_tag, false);
|
||||
snd_hdac_ext_stream_release(estream, HDAC_EXT_STREAM_TYPE_HOST);
|
||||
|
||||
snd_hdac_dsp_cleanup(stream, dmab);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct skl_dsp_loader_ops skl_get_loader_ops(void)
|
||||
{
|
||||
struct skl_dsp_loader_ops loader_ops;
|
||||
|
|
@ -84,6 +183,21 @@ static struct skl_dsp_loader_ops skl_get_loader_ops(void)
|
|||
return loader_ops;
|
||||
};
|
||||
|
||||
static struct skl_dsp_loader_ops bxt_get_loader_ops(void)
|
||||
{
|
||||
struct skl_dsp_loader_ops loader_ops;
|
||||
|
||||
memset(&loader_ops, 0, sizeof(loader_ops));
|
||||
|
||||
loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
|
||||
loader_ops.free_dma_buf = skl_free_dma_buf;
|
||||
loader_ops.prepare = skl_dsp_prepare;
|
||||
loader_ops.trigger = skl_dsp_trigger;
|
||||
loader_ops.cleanup = skl_dsp_cleanup;
|
||||
|
||||
return loader_ops;
|
||||
};
|
||||
|
||||
static const struct skl_dsp_ops dsp_ops[] = {
|
||||
{
|
||||
.id = 0x9d70,
|
||||
|
|
@ -91,6 +205,12 @@ static const struct skl_dsp_ops dsp_ops[] = {
|
|||
.init = skl_sst_dsp_init,
|
||||
.cleanup = skl_sst_dsp_cleanup
|
||||
},
|
||||
{
|
||||
.id = 0x5a98,
|
||||
.loader_ops = bxt_get_loader_ops,
|
||||
.init = bxt_sst_dsp_init,
|
||||
.cleanup = bxt_sst_dsp_cleanup
|
||||
},
|
||||
};
|
||||
|
||||
static int skl_get_dsp_ops(int pci_id)
|
||||
|
|
|
|||
|
|
@ -124,10 +124,19 @@ struct skl_dsp_fw_ops {
|
|||
};
|
||||
|
||||
struct skl_dsp_loader_ops {
|
||||
int stream_tag;
|
||||
|
||||
int (*alloc_dma_buf)(struct device *dev,
|
||||
struct snd_dma_buffer *dmab, size_t size);
|
||||
int (*free_dma_buf)(struct device *dev,
|
||||
struct snd_dma_buffer *dmab);
|
||||
int (*prepare)(struct device *dev, unsigned int format,
|
||||
unsigned int byte_size,
|
||||
struct snd_dma_buffer *bufp);
|
||||
int (*trigger)(struct device *dev, bool start, int stream_tag);
|
||||
|
||||
int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
|
||||
int stream_tag);
|
||||
};
|
||||
|
||||
struct skl_load_module_info {
|
||||
|
|
@ -160,6 +169,10 @@ int skl_dsp_boot(struct sst_dsp *ctx);
|
|||
int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
|
||||
const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
|
||||
struct skl_sst **dsp);
|
||||
int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
|
||||
const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
|
||||
struct skl_sst **dsp);
|
||||
void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
|
||||
void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
|
||||
|
||||
#endif /*__SKL_SST_DSP_H__*/
|
||||
|
|
|
|||
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