memory: tegra30-emc: Poll EMC-CaR handshake instead of waiting for interrupt
The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko
Thierry Reding
Родитель
adbcec8862
Коммит
930c68180f
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@ -11,7 +11,6 @@
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/completion.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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@ -327,7 +326,6 @@ struct emc_timing {
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struct tegra_emc {
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struct device *dev;
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struct tegra_mc *mc;
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struct completion clk_handshake_complete;
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struct notifier_block clk_nb;
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struct clk *clk;
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void __iomem *regs;
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@ -374,52 +372,10 @@ static int emc_seq_update_timing(struct tegra_emc *emc)
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return 0;
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}
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static void emc_complete_clk_change(struct tegra_emc *emc)
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{
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struct emc_timing *timing = emc->new_timing;
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unsigned int dram_num;
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bool failed = false;
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int err;
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/* re-enable auto-refresh */
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dram_num = tegra_mc_get_emem_device_count(emc->mc);
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writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
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emc->regs + EMC_REFCTRL);
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/* restore auto-calibration */
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if (emc->vref_cal_toggle)
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writel_relaxed(timing->emc_auto_cal_interval,
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emc->regs + EMC_AUTO_CAL_INTERVAL);
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/* restore dynamic self-refresh */
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if (timing->emc_cfg_dyn_self_ref) {
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emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
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writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
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}
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/* set number of clocks to wait after each ZQ command */
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if (emc->zcal_long)
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writel_relaxed(timing->emc_zcal_cnt_long,
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emc->regs + EMC_ZCAL_WAIT_CNT);
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/* wait for writes to settle */
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udelay(2);
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/* update restored timing */
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err = emc_seq_update_timing(emc);
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if (err)
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failed = true;
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/* restore early ACK */
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mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
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WRITE_ONCE(emc->bad_state, failed);
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}
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static irqreturn_t tegra_emc_isr(int irq, void *data)
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{
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struct tegra_emc *emc = data;
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u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
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u32 intmask = EMC_REFRESH_OVERFLOW_INT;
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u32 status;
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status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
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@ -434,18 +390,6 @@ static irqreturn_t tegra_emc_isr(int irq, void *data)
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/* clear interrupts */
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writel_relaxed(status, emc->regs + EMC_INTSTATUS);
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/* notify about EMC-CAR handshake completion */
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if (status & EMC_CLKCHANGE_COMPLETE_INT) {
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if (completion_done(&emc->clk_handshake_complete)) {
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dev_err_ratelimited(emc->dev,
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"bogus handshake interrupt\n");
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return IRQ_NONE;
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}
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emc_complete_clk_change(emc);
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complete(&emc->clk_handshake_complete);
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}
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return IRQ_HANDLED;
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}
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@ -801,29 +745,58 @@ static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
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*/
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mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
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reinit_completion(&emc->clk_handshake_complete);
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emc->new_timing = timing;
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return 0;
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}
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static int emc_complete_timing_change(struct tegra_emc *emc,
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unsigned long rate)
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{
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unsigned long timeout;
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struct emc_timing *timing = emc_find_timing(emc, rate);
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unsigned int dram_num;
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int err;
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u32 v;
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timeout = wait_for_completion_timeout(&emc->clk_handshake_complete,
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msecs_to_jiffies(100));
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if (timeout == 0) {
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dev_err(emc->dev, "emc-car handshake failed\n");
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return -EIO;
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err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
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v & EMC_CLKCHANGE_COMPLETE_INT,
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1, 100);
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if (err) {
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dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
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return err;
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}
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if (READ_ONCE(emc->bad_state))
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return -EIO;
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/* re-enable auto-refresh */
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dram_num = tegra_mc_get_emem_device_count(emc->mc);
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writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
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emc->regs + EMC_REFCTRL);
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return 0;
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/* restore auto-calibration */
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if (emc->vref_cal_toggle)
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writel_relaxed(timing->emc_auto_cal_interval,
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emc->regs + EMC_AUTO_CAL_INTERVAL);
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/* restore dynamic self-refresh */
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if (timing->emc_cfg_dyn_self_ref) {
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emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
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writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
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}
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/* set number of clocks to wait after each ZQ command */
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if (emc->zcal_long)
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writel_relaxed(timing->emc_zcal_cnt_long,
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emc->regs + EMC_ZCAL_WAIT_CNT);
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/* wait for writes to settle */
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udelay(2);
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/* update restored timing */
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err = emc_seq_update_timing(emc);
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if (!err)
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emc->bad_state = false;
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/* restore early ACK */
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mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
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return err;
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}
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static int emc_unprepare_timing_change(struct tegra_emc *emc,
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@ -1033,7 +1006,7 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev)
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static int emc_setup_hw(struct tegra_emc *emc)
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{
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u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
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u32 intmask = EMC_REFRESH_OVERFLOW_INT;
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u32 fbio_cfg5, emc_cfg, emc_dbg;
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enum emc_dram_type dram_type;
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@ -1321,7 +1294,6 @@ static int tegra_emc_probe(struct platform_device *pdev)
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if (!emc->mc)
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return -EPROBE_DEFER;
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init_completion(&emc->clk_handshake_complete);
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emc->clk_nb.notifier_call = emc_clk_change_notify;
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emc->dev = &pdev->dev;
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